1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * SBC8641D board configuration file 31 * 32 * Make sure you change the MAC address and other network params first, 33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 34 */ 35 36 #ifndef __CONFIG_H 37 #define __CONFIG_H 38 39 /* High Level Configuration Options */ 40 #define CONFIG_MPC86xx 1 /* MPC86xx */ 41 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 43 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 44 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 45 46 #ifdef RUN_DIAG 47 #define CFG_DIAG_ADDR 0xff800000 48 #endif 49 50 #define CFG_RESET_ADDRESS 0xfff00100 51 52 #undef CONFIG_PCI 53 #define CONFIG_FSL_PCI_INIT 1 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 59 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 60 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 61 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 63 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 64 #define CONFIG_NUM_DDR_CONTROLLERS 2 65 #define CACHE_LINE_INTERLEAVING 0x20000000 66 #define PAGE_INTERLEAVING 0x21000000 67 #define BANK_INTERLEAVING 0x22000000 68 #define SUPER_BANK_INTERLEAVING 0x23000000 69 70 71 #define CONFIG_ALTIVEC 1 72 73 /* 74 * L2CR setup -- make sure this is right for your board! 75 */ 76 #define CFG_L2 77 #define L2_INIT 0 78 #define L2_ENABLE (L2CR_L2E) 79 80 #ifndef CONFIG_SYS_CLK_FREQ 81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 82 #endif 83 84 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 85 86 #undef CFG_DRAM_TEST /* memory test, takes time */ 87 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 88 #define CFG_MEMTEST_END 0x00400000 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 95 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 96 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 102 #define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 103 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 104 #define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 105 #define CONFIG_VERY_BIG_RAM 106 107 #define MPC86xx_DDR_SDRAM_CLK_CNTL 108 109 #if defined(CONFIG_SPD_EEPROM) 110 /* 111 * Determine DDR configuration from I2C interface. 112 */ 113 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 114 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 115 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 116 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 117 118 #else 119 /* 120 * Manually set up DDR1 & DDR2 parameters 121 */ 122 123 #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ 124 125 #define CFG_DDR_CS0_BNDS 0x0000000F 126 #define CFG_DDR_CS1_BNDS 0x00000000 127 #define CFG_DDR_CS2_BNDS 0x00000000 128 #define CFG_DDR_CS3_BNDS 0x00000000 129 #define CFG_DDR_CS0_CONFIG 0x80010102 130 #define CFG_DDR_CS1_CONFIG 0x00000000 131 #define CFG_DDR_CS2_CONFIG 0x00000000 132 #define CFG_DDR_CS3_CONFIG 0x00000000 133 #define CFG_DDR_EXT_REFRESH 0x00000000 134 #define CFG_DDR_TIMING_0 0x00220802 135 #define CFG_DDR_TIMING_1 0x38377322 136 #define CFG_DDR_TIMING_2 0x002040c7 137 #define CFG_DDR_CFG_1A 0x43008008 138 #define CFG_DDR_CFG_2 0x24401000 139 #define CFG_DDR_MODE_1 0x23c00542 140 #define CFG_DDR_MODE_2 0x00000000 141 #define CFG_DDR_MODE_CTL 0x00000000 142 #define CFG_DDR_INTERVAL 0x05080100 143 #define CFG_DDR_DATA_INIT 0x00000000 144 #define CFG_DDR_CLK_CTRL 0x03800000 145 #define CFG_DDR_CFG_1B 0xC3008008 146 147 #define CFG_DDR2_CS0_BNDS 0x0010001F 148 #define CFG_DDR2_CS1_BNDS 0x00000000 149 #define CFG_DDR2_CS2_BNDS 0x00000000 150 #define CFG_DDR2_CS3_BNDS 0x00000000 151 #define CFG_DDR2_CS0_CONFIG 0x80010102 152 #define CFG_DDR2_CS1_CONFIG 0x00000000 153 #define CFG_DDR2_CS2_CONFIG 0x00000000 154 #define CFG_DDR2_CS3_CONFIG 0x00000000 155 #define CFG_DDR2_EXT_REFRESH 0x00000000 156 #define CFG_DDR2_TIMING_0 0x00220802 157 #define CFG_DDR2_TIMING_1 0x38377322 158 #define CFG_DDR2_TIMING_2 0x002040c7 159 #define CFG_DDR2_CFG_1A 0x43008008 160 #define CFG_DDR2_CFG_2 0x24401000 161 #define CFG_DDR2_MODE_1 0x23c00542 162 #define CFG_DDR2_MODE_2 0x00000000 163 #define CFG_DDR2_MODE_CTL 0x00000000 164 #define CFG_DDR2_INTERVAL 0x05080100 165 #define CFG_DDR2_DATA_INIT 0x00000000 166 #define CFG_DDR2_CLK_CTRL 0x03800000 167 #define CFG_DDR2_CFG_1B 0xC3008008 168 169 170 #endif 171 172 /* #define CFG_ID_EEPROM 1 173 #define ID_EEPROM_ADDR 0x57 */ 174 175 /* 176 * The SBC8641D contains 16MB flash space at ff000000. 177 */ 178 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 179 180 /* Flash */ 181 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 182 #define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 183 184 /* 64KB EEPROM */ 185 #define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ 186 #define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 187 188 /* EPLD - User switches, board id, LEDs */ 189 #define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ 190 #define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 191 192 /* Local bus SDRAM 128MB */ 193 #define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ 194 #define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 195 #define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ 196 #define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 197 198 /* Disk on Chip (DOC) 128MB */ 199 #define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ 200 #define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 201 202 /* LCD */ 203 #define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ 204 #define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 205 206 /* Control logic & misc peripherals */ 207 #define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ 208 #define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 209 210 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 211 #define CFG_MAX_FLASH_SECT 131 /* sectors per device */ 212 213 #undef CFG_FLASH_CHECKSUM 214 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 215 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 216 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 217 218 #define CFG_FLASH_CFI_DRIVER 219 #define CFG_FLASH_CFI 220 #define CFG_WRITE_SWAPPED_DATA 221 #define CFG_FLASH_EMPTY_INFO 222 #define CFG_FLASH_PROTECTION 223 224 #undef CONFIG_CLOCKS_IN_MHZ 225 226 #define CONFIG_L1_INIT_RAM 227 #define CFG_INIT_RAM_LOCK 1 228 #ifndef CFG_INIT_RAM_LOCK 229 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 230 #else 231 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 232 #endif 233 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 234 235 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 236 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 237 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 238 239 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 240 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 241 242 /* Serial Port */ 243 #define CONFIG_CONS_INDEX 1 244 #undef CONFIG_SERIAL_SOFTWARE_FIFO 245 #define CFG_NS16550 246 #define CFG_NS16550_SERIAL 247 #define CFG_NS16550_REG_SIZE 1 248 #define CFG_NS16550_CLK get_bus_freq(0) 249 250 #define CFG_BAUDRATE_TABLE \ 251 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 252 253 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 254 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 255 256 /* Use the HUSH parser */ 257 #define CFG_HUSH_PARSER 258 #ifdef CFG_HUSH_PARSER 259 #define CFG_PROMPT_HUSH_PS2 "> " 260 #endif 261 262 /* 263 * Pass open firmware flat tree to kernel 264 */ 265 #define CONFIG_OF_FLAT_TREE 1 266 #define CONFIG_OF_BOARD_SETUP 1 267 268 /* maximum size of the flat tree (8K) */ 269 #define OF_FLAT_TREE_MAX_SIZE 8192 270 271 #define OF_CPU "PowerPC,8641@0" 272 #define OF_SOC "soc@f8000000" 273 #define OF_TBCLK (bd->bi_busfreq / 4) 274 #define OF_STDOUT_PATH "/soc@f8000000/serial@4500" 275 276 #define CFG_64BIT_VSPRINTF 1 277 #define CFG_64BIT_STRTOUL 1 278 279 /* 280 * I2C 281 */ 282 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 283 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 284 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 285 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 286 #define CFG_I2C_SLAVE 0x7F 287 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 288 #define CFG_I2C_OFFSET 0x3100 289 290 /* 291 * RapidIO MMU 292 */ 293 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 294 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 295 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 296 297 /* 298 * General PCI 299 * Addresses are mapped 1-1. 300 */ 301 #define CFG_PCI1_MEM_BASE 0x80000000 302 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 303 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 304 #define CFG_PCI1_IO_BASE 0xe2000000 305 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 306 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 307 308 /* PCI view of System Memory */ 309 #define CFG_PCI_MEMORY_BUS 0x00000000 310 #define CFG_PCI_MEMORY_PHYS 0x00000000 311 #define CFG_PCI_MEMORY_SIZE 0x80000000 312 313 #define CFG_PCI2_MEM_BASE 0xa0000000 314 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 315 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 316 #define CFG_PCI2_IO_BASE 0xe3000000 317 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 318 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 319 320 #if defined(CONFIG_PCI) 321 322 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 323 324 #undef CFG_SCSI_SCAN_BUS_REVERSE 325 326 #define CONFIG_NET_MULTI 327 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 328 329 #undef CONFIG_EEPRO100 330 #undef CONFIG_TULIP 331 332 #if !defined(CONFIG_PCI_PNP) 333 #define PCI_ENET0_IOADDR 0xe0000000 334 #define PCI_ENET0_MEMADDR 0xe0000000 335 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 336 #endif 337 338 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 339 340 #define CONFIG_DOS_PARTITION 341 #undef CONFIG_SCSI_AHCI 342 343 #ifdef CONFIG_SCSI_AHCI 344 #define CONFIG_SATA_ULI5288 345 #define CFG_SCSI_MAX_SCSI_ID 4 346 #define CFG_SCSI_MAX_LUN 1 347 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 348 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 349 #endif 350 351 #endif /* CONFIG_PCI */ 352 353 #if defined(CONFIG_TSEC_ENET) 354 355 #ifndef CONFIG_NET_MULTI 356 #define CONFIG_NET_MULTI 1 357 #endif 358 359 /* #define CONFIG_MII 1 */ /* MII PHY management */ 360 361 #define CONFIG_TSEC1 1 362 #define CONFIG_TSEC1_NAME "eTSEC1" 363 #define CONFIG_TSEC2 1 364 #define CONFIG_TSEC2_NAME "eTSEC2" 365 #define CONFIG_TSEC3 1 366 #define CONFIG_TSEC3_NAME "eTSEC3" 367 #define CONFIG_TSEC4 1 368 #define CONFIG_TSEC4_NAME "eTSEC4" 369 370 #define TSEC1_PHY_ADDR 0x1F 371 #define TSEC2_PHY_ADDR 0x00 372 #define TSEC3_PHY_ADDR 0x01 373 #define TSEC4_PHY_ADDR 0x02 374 #define TSEC1_PHYIDX 0 375 #define TSEC2_PHYIDX 0 376 #define TSEC3_PHYIDX 0 377 #define TSEC4_PHYIDX 0 378 379 #define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 380 381 #define CONFIG_ETHPRIME "eTSEC1" 382 383 #endif /* CONFIG_TSEC_ENET */ 384 385 /* 386 * BAT0 2G Cacheable, non-guarded 387 * 0x0000_0000 2G DDR 388 */ 389 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 390 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 391 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 392 #define CFG_IBAT0U CFG_DBAT0U 393 394 /* 395 * BAT1 1G Cache-inhibited, guarded 396 * 0x8000_0000 512M PCI-Express 1 Memory 397 * 0xa000_0000 512M PCI-Express 2 Memory 398 * Changed it for operating from 0xd0000000 399 */ 400 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ 401 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 402 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 403 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 404 #define CFG_IBAT1U CFG_DBAT1U 405 406 /* 407 * BAT2 512M Cache-inhibited, guarded 408 * 0xc000_0000 512M RapidIO Memory 409 */ 410 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ 411 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 412 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 413 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 414 #define CFG_IBAT2U CFG_DBAT2U 415 416 /* 417 * BAT3 4M Cache-inhibited, guarded 418 * 0xf800_0000 4M CCSR 419 */ 420 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 421 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 422 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 423 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 424 #define CFG_IBAT3U CFG_DBAT3U 425 426 /* 427 * BAT4 32M Cache-inhibited, guarded 428 * 0xe200_0000 16M PCI-Express 1 I/O 429 * 0xe300_0000 16M PCI-Express 2 I/0 430 * Note that this is at 0xe0000000 431 */ 432 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ 433 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 434 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 435 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 436 #define CFG_IBAT4U CFG_DBAT4U 437 438 /* 439 * BAT5 128K Cacheable, non-guarded 440 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 441 */ 442 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 443 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 444 #define CFG_IBAT5L CFG_DBAT5L 445 #define CFG_IBAT5U CFG_DBAT5U 446 447 /* 448 * BAT6 32M Cache-inhibited, guarded 449 * 0xfe00_0000 32M FLASH 450 */ 451 #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 452 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 453 #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 454 #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 455 #define CFG_IBAT6U CFG_DBAT6U 456 457 #define CFG_DBAT7L 0x00000000 458 #define CFG_DBAT7U 0x00000000 459 #define CFG_IBAT7L 0x00000000 460 #define CFG_IBAT7U 0x00000000 461 462 /* 463 * Environment 464 */ 465 #define CFG_ENV_IS_IN_FLASH 1 466 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 467 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 468 #define CFG_ENV_SIZE 0x2000 469 470 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 471 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 472 473 #include <config_cmd_default.h> 474 #define CONFIG_CMD_PING 475 #define CONFIG_CMD_I2C 476 477 #if defined(CONFIG_PCI) 478 #define CONFIG_CMD_PCI 479 #endif 480 481 #undef CONFIG_WATCHDOG /* watchdog disabled */ 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 #define CFG_LONGHELP /* undef to save memory */ 487 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 488 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 489 490 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 491 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 492 #else 493 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 494 #endif 495 496 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 497 #define CFG_MAXARGS 16 /* max number of command args */ 498 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 499 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 500 501 /* 502 * For booting Linux, the board info and command line data 503 * have to be in the first 8 MB of memory, since this is 504 * the maximum mapped by the Linux kernel during initialization. 505 */ 506 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 507 508 /* Cache Configuration */ 509 #define CFG_DCACHE_SIZE 32768 510 #define CFG_CACHELINE_SIZE 32 511 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 512 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 513 #endif 514 515 /* 516 * Internal Definitions 517 * 518 * Boot Flags 519 */ 520 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 521 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 522 523 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 525 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 526 #endif 527 528 /* 529 * Environment Configuration 530 */ 531 532 /* The mac addresses for all ethernet interface */ 533 #if defined(CONFIG_TSEC_ENET) 534 #define CONFIG_ETHADDR 02:E0:0C:00:00:01 535 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 536 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 537 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 538 #endif 539 540 #define CONFIG_HAS_ETH1 1 541 #define CONFIG_HAS_ETH2 1 542 #define CONFIG_HAS_ETH3 1 543 544 #define CONFIG_IPADDR 192.168.0.50 545 546 #define CONFIG_HOSTNAME sbc8641d 547 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx 548 #define CONFIG_BOOTFILE uImage 549 550 #define CONFIG_SERVERIP 192.168.0.2 551 #define CONFIG_GATEWAYIP 192.168.0.1 552 #define CONFIG_NETMASK 255.255.255.0 553 554 /* default location for tftp and bootm */ 555 #define CONFIG_LOADADDR 1000000 556 557 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 558 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 559 560 #define CONFIG_BAUDRATE 115200 561 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "netdev=eth0\0" \ 564 "consoledev=ttyS0\0" \ 565 "ramdiskaddr=2000000\0" \ 566 "ramdiskfile=uRamdisk\0" \ 567 "dtbaddr=400000\0" \ 568 "dtbfile=sbc8641d.dtb\0" \ 569 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 570 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 571 "maxcpus=1" 572 573 #define CONFIG_NFSBOOTCOMMAND \ 574 "setenv bootargs root=/dev/nfs rw " \ 575 "nfsroot=$serverip:$rootpath " \ 576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 577 "console=$consoledev,$baudrate $othbootargs;" \ 578 "tftp $loadaddr $bootfile;" \ 579 "tftp $dtbaddr $dtbfile;" \ 580 "bootm $loadaddr - $dtbaddr" 581 582 #define CONFIG_RAMBOOTCOMMAND \ 583 "setenv bootargs root=/dev/ram rw " \ 584 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 585 "console=$consoledev,$baudrate $othbootargs;" \ 586 "tftp $ramdiskaddr $ramdiskfile;" \ 587 "tftp $loadaddr $bootfile;" \ 588 "tftp $dtbaddr $dtbfile;" \ 589 "bootm $loadaddr $ramdiskaddr $dtbaddr" 590 591 #define CONFIG_FLASHBOOTCOMMAND \ 592 "setenv bootargs root=/dev/ram rw " \ 593 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 594 "console=$consoledev,$baudrate $othbootargs;" \ 595 "bootm ffd00000 ffb00000 ffa00000" 596 597 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 598 599 #endif /* __CONFIG_H */ 600