1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 25 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 26 #define CONFIG_MP 1 /* support multiple processors */ 27 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 28 29 #define CONFIG_SYS_TEXT_BASE 0xfff00000 30 31 #ifdef RUN_DIAG 32 #define CONFIG_SYS_DIAG_ADDR 0xff800000 33 #endif 34 35 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 36 37 /* 38 * virtual address to be used for temporary mappings. There 39 * should be 128k free at this VA. 40 */ 41 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 47 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 48 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 49 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 50 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 51 52 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 53 #define CONFIG_ENV_OVERWRITE 54 55 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 56 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 57 58 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 59 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 60 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 61 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 62 #define CONFIG_NUM_DDR_CONTROLLERS 2 63 #define CACHE_LINE_INTERLEAVING 0x20000000 64 #define PAGE_INTERLEAVING 0x21000000 65 #define BANK_INTERLEAVING 0x22000000 66 #define SUPER_BANK_INTERLEAVING 0x23000000 67 68 #define CONFIG_ALTIVEC 1 69 70 /* 71 * L2CR setup -- make sure this is right for your board! 72 */ 73 #define CONFIG_SYS_L2 74 #define L2_INIT 0 75 #define L2_ENABLE (L2CR_L2E) 76 77 #ifndef CONFIG_SYS_CLK_FREQ 78 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 79 #endif 80 81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 82 83 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 84 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 85 #define CONFIG_SYS_MEMTEST_END 0x00400000 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 92 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 93 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 94 95 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 96 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 97 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 98 99 /* 100 * DDR Setup 101 */ 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 103 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 106 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 107 #define CONFIG_VERY_BIG_RAM 108 109 #define CONFIG_NUM_DDR_CONTROLLERS 2 110 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 111 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 112 113 #if defined(CONFIG_SPD_EEPROM) 114 /* 115 * Determine DDR configuration from I2C interface. 116 */ 117 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 118 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 119 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 120 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 121 122 #else 123 /* 124 * Manually set up DDR1 & DDR2 parameters 125 */ 126 127 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 128 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 130 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 131 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 132 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 133 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 134 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 135 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 136 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 139 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 140 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 141 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 142 #define CONFIG_SYS_DDR_CFG_2 0x24401000 143 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 144 #define CONFIG_SYS_DDR_MODE_2 0x00000000 145 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 146 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 147 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 148 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 149 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 150 151 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 152 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 153 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 154 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 155 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 156 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 157 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 158 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 159 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 160 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 161 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 162 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 163 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 164 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 165 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 166 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 167 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 168 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 169 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 170 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 171 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 172 173 #endif 174 175 /* #define CONFIG_ID_EEPROM 1 176 #define ID_EEPROM_ADDR 0x57 */ 177 178 /* 179 * The SBC8641D contains 16MB flash space at ff000000. 180 */ 181 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 182 183 /* Flash */ 184 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 185 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 186 187 /* 64KB EEPROM */ 188 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 189 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 190 191 /* EPLD - User switches, board id, LEDs */ 192 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 193 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 194 195 /* Local bus SDRAM 128MB */ 196 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 197 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 198 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 199 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 200 201 /* Disk on Chip (DOC) 128MB */ 202 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 203 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 204 205 /* LCD */ 206 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 207 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 208 209 /* Control logic & misc peripherals */ 210 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 211 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 212 213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 214 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 215 216 #undef CONFIG_SYS_FLASH_CHECKSUM 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 220 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 221 222 #define CONFIG_FLASH_CFI_DRIVER 223 #define CONFIG_SYS_FLASH_CFI 224 #define CONFIG_SYS_WRITE_SWAPPED_DATA 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 #define CONFIG_SYS_FLASH_PROTECTION 227 228 #undef CONFIG_CLOCKS_IN_MHZ 229 230 #define CONFIG_SYS_INIT_RAM_LOCK 1 231 #ifndef CONFIG_SYS_INIT_RAM_LOCK 232 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 233 #else 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 235 #endif 236 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 237 238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 240 241 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 242 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 243 244 /* Serial Port */ 245 #define CONFIG_CONS_INDEX 1 246 #define CONFIG_SYS_NS16550_SERIAL 247 #define CONFIG_SYS_NS16550_REG_SIZE 1 248 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 249 250 #define CONFIG_SYS_BAUDRATE_TABLE \ 251 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 252 253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 255 256 /* 257 * I2C 258 */ 259 #define CONFIG_SYS_I2C 260 #define CONFIG_SYS_I2C_FSL 261 #define CONFIG_SYS_FSL_I2C_SPEED 400000 262 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 263 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 264 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 265 266 /* 267 * RapidIO MMU 268 */ 269 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 270 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 271 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 272 273 /* 274 * General PCI 275 * Addresses are mapped 1-1. 276 */ 277 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 278 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 279 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 280 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 281 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 282 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 283 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 284 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 285 286 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 287 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 288 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 289 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 290 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 291 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 292 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 293 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 294 295 #if defined(CONFIG_PCI) 296 297 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 298 299 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 300 301 #undef CONFIG_EEPRO100 302 #undef CONFIG_TULIP 303 304 #if !defined(CONFIG_PCI_PNP) 305 #define PCI_ENET0_IOADDR 0xe0000000 306 #define PCI_ENET0_MEMADDR 0xe0000000 307 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 308 #endif 309 310 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 311 312 #define CONFIG_DOS_PARTITION 313 #undef CONFIG_SCSI_AHCI 314 315 #ifdef CONFIG_SCSI_AHCI 316 #define CONFIG_SATA_ULI5288 317 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 318 #define CONFIG_SYS_SCSI_MAX_LUN 1 319 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 320 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 321 #endif 322 323 #endif /* CONFIG_PCI */ 324 325 #if defined(CONFIG_TSEC_ENET) 326 327 /* #define CONFIG_MII 1 */ /* MII PHY management */ 328 329 #define CONFIG_TSEC1 1 330 #define CONFIG_TSEC1_NAME "eTSEC1" 331 #define CONFIG_TSEC2 1 332 #define CONFIG_TSEC2_NAME "eTSEC2" 333 #define CONFIG_TSEC3 1 334 #define CONFIG_TSEC3_NAME "eTSEC3" 335 #define CONFIG_TSEC4 1 336 #define CONFIG_TSEC4_NAME "eTSEC4" 337 338 #define TSEC1_PHY_ADDR 0x1F 339 #define TSEC2_PHY_ADDR 0x00 340 #define TSEC3_PHY_ADDR 0x01 341 #define TSEC4_PHY_ADDR 0x02 342 #define TSEC1_PHYIDX 0 343 #define TSEC2_PHYIDX 0 344 #define TSEC3_PHYIDX 0 345 #define TSEC4_PHYIDX 0 346 #define TSEC1_FLAGS TSEC_GIGABIT 347 #define TSEC2_FLAGS TSEC_GIGABIT 348 #define TSEC3_FLAGS TSEC_GIGABIT 349 #define TSEC4_FLAGS TSEC_GIGABIT 350 351 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 352 353 #define CONFIG_ETHPRIME "eTSEC1" 354 355 #endif /* CONFIG_TSEC_ENET */ 356 357 /* 358 * BAT0 2G Cacheable, non-guarded 359 * 0x0000_0000 2G DDR 360 */ 361 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 362 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 363 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 364 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 365 366 /* 367 * BAT1 1G Cache-inhibited, guarded 368 * 0x8000_0000 512M PCI-Express 1 Memory 369 * 0xa000_0000 512M PCI-Express 2 Memory 370 * Changed it for operating from 0xd0000000 371 */ 372 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 373 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 374 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 375 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 376 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 377 378 /* 379 * BAT2 512M Cache-inhibited, guarded 380 * 0xc000_0000 512M RapidIO Memory 381 */ 382 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 383 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 385 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 386 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 387 388 /* 389 * BAT3 4M Cache-inhibited, guarded 390 * 0xf800_0000 4M CCSR 391 */ 392 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 393 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 394 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 395 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 396 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 397 398 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 399 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 400 | BATL_PP_RW | BATL_CACHEINHIBIT \ 401 | BATL_GUARDEDSTORAGE) 402 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 403 | BATU_BL_1M | BATU_VS | BATU_VP) 404 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 405 | BATL_PP_RW | BATL_CACHEINHIBIT) 406 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 407 #endif 408 409 /* 410 * BAT4 32M Cache-inhibited, guarded 411 * 0xe200_0000 16M PCI-Express 1 I/O 412 * 0xe300_0000 16M PCI-Express 2 I/0 413 * Note that this is at 0xe0000000 414 */ 415 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 416 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 417 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 418 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 419 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 420 421 /* 422 * BAT5 128K Cacheable, non-guarded 423 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 424 */ 425 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 426 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 427 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 428 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 429 430 /* 431 * BAT6 32M Cache-inhibited, guarded 432 * 0xfe00_0000 32M FLASH 433 */ 434 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 435 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 438 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 439 440 /* Map the last 1M of flash where we're running from reset */ 441 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 442 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 443 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 444 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 445 | BATL_MEMCOHERENCE) 446 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 447 448 #define CONFIG_SYS_DBAT7L 0x00000000 449 #define CONFIG_SYS_DBAT7U 0x00000000 450 #define CONFIG_SYS_IBAT7L 0x00000000 451 #define CONFIG_SYS_IBAT7U 0x00000000 452 453 /* 454 * Environment 455 */ 456 #define CONFIG_ENV_IS_IN_FLASH 1 457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 458 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 459 #define CONFIG_ENV_SIZE 0x2000 460 461 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 462 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 463 464 #define CONFIG_CMD_REGINFO 465 466 #if defined(CONFIG_PCI) 467 #define CONFIG_CMD_PCI 468 #endif 469 470 #undef CONFIG_WATCHDOG /* watchdog disabled */ 471 472 /* 473 * Miscellaneous configurable options 474 */ 475 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 476 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 477 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 478 479 #if defined(CONFIG_CMD_KGDB) 480 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 481 #else 482 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 483 #endif 484 485 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 486 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 487 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 488 489 /* 490 * For booting Linux, the board info and command line data 491 * have to be in the first 8 MB of memory, since this is 492 * the maximum mapped by the Linux kernel during initialization. 493 */ 494 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 495 496 /* Cache Configuration */ 497 #define CONFIG_SYS_DCACHE_SIZE 32768 498 #define CONFIG_SYS_CACHELINE_SIZE 32 499 #if defined(CONFIG_CMD_KGDB) 500 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 501 #endif 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 505 #endif 506 507 /* 508 * Environment Configuration 509 */ 510 511 #define CONFIG_HAS_ETH0 1 512 #define CONFIG_HAS_ETH1 1 513 #define CONFIG_HAS_ETH2 1 514 #define CONFIG_HAS_ETH3 1 515 516 #define CONFIG_IPADDR 192.168.0.50 517 518 #define CONFIG_HOSTNAME sbc8641d 519 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 520 #define CONFIG_BOOTFILE "uImage" 521 522 #define CONFIG_SERVERIP 192.168.0.2 523 #define CONFIG_GATEWAYIP 192.168.0.1 524 #define CONFIG_NETMASK 255.255.255.0 525 526 /* default location for tftp and bootm */ 527 #define CONFIG_LOADADDR 1000000 528 529 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 530 531 #define CONFIG_BAUDRATE 115200 532 533 #define CONFIG_EXTRA_ENV_SETTINGS \ 534 "netdev=eth0\0" \ 535 "consoledev=ttyS0\0" \ 536 "ramdiskaddr=2000000\0" \ 537 "ramdiskfile=uRamdisk\0" \ 538 "dtbaddr=400000\0" \ 539 "dtbfile=sbc8641d.dtb\0" \ 540 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 541 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 542 "maxcpus=1" 543 544 #define CONFIG_NFSBOOTCOMMAND \ 545 "setenv bootargs root=/dev/nfs rw " \ 546 "nfsroot=$serverip:$rootpath " \ 547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548 "console=$consoledev,$baudrate $othbootargs;" \ 549 "tftp $loadaddr $bootfile;" \ 550 "tftp $dtbaddr $dtbfile;" \ 551 "bootm $loadaddr - $dtbaddr" 552 553 #define CONFIG_RAMBOOTCOMMAND \ 554 "setenv bootargs root=/dev/ram rw " \ 555 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $ramdiskaddr $ramdiskfile;" \ 558 "tftp $loadaddr $bootfile;" \ 559 "tftp $dtbaddr $dtbfile;" \ 560 "bootm $loadaddr $ramdiskaddr $dtbaddr" 561 562 #define CONFIG_FLASHBOOTCOMMAND \ 563 "setenv bootargs root=/dev/ram rw " \ 564 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 565 "console=$consoledev,$baudrate $othbootargs;" \ 566 "bootm ffd00000 ffb00000 ffa00000" 567 568 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 569 570 #endif /* __CONFIG_H */ 571