1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * SBC8641D board configuration file 31 * 32 * Make sure you change the MAC address and other network params first, 33 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 34 */ 35 36 #ifndef __CONFIG_H 37 #define __CONFIG_H 38 39 /* High Level Configuration Options */ 40 #define CONFIG_MPC86xx 1 /* MPC86xx */ 41 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 42 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 43 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 44 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 45 46 #ifdef RUN_DIAG 47 #define CONFIG_SYS_DIAG_ADDR 0xff800000 48 #endif 49 50 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 51 52 /* 53 * virtual address to be used for temporary mappings. There 54 * should be 128k free at this VA. 55 */ 56 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 57 58 #define CONFIG_PCI 1 /* Enable PCIE */ 59 #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ 60 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ 61 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 62 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 63 64 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 68 69 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 70 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 #define CONFIG_NUM_DDR_CONTROLLERS 2 74 #define CACHE_LINE_INTERLEAVING 0x20000000 75 #define PAGE_INTERLEAVING 0x21000000 76 #define BANK_INTERLEAVING 0x22000000 77 #define SUPER_BANK_INTERLEAVING 0x23000000 78 79 80 #define CONFIG_ALTIVEC 1 81 82 /* 83 * L2CR setup -- make sure this is right for your board! 84 */ 85 #define CONFIG_SYS_L2 86 #define L2_INIT 0 87 #define L2_ENABLE (L2CR_L2E) 88 89 #ifndef CONFIG_SYS_CLK_FREQ 90 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 91 #endif 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 99 /* 100 * Base addresses -- Note these are effective addresses where the 101 * actual resources get mapped (not physical addresses) 102 */ 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 104 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 105 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 106 107 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 108 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 109 110 /* 111 * DDR Setup 112 */ 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 114 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 116 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 117 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 118 #define CONFIG_VERY_BIG_RAM 119 120 #define MPC86xx_DDR_SDRAM_CLK_CNTL 121 122 #define CONFIG_NUM_DDR_CONTROLLERS 2 123 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 124 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 125 126 #if defined(CONFIG_SPD_EEPROM) 127 /* 128 * Determine DDR configuration from I2C interface. 129 */ 130 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 131 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 132 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 133 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 134 135 #else 136 /* 137 * Manually set up DDR1 & DDR2 parameters 138 */ 139 140 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 141 142 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 143 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 144 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 145 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 146 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 147 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 148 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 149 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 150 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 151 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 152 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 153 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 154 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 155 #define CONFIG_SYS_DDR_CFG_2 0x24401000 156 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 157 #define CONFIG_SYS_DDR_MODE_2 0x00000000 158 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 159 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 160 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 161 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 162 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 163 164 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 165 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 166 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 167 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 168 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 169 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 170 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 171 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 172 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 173 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 174 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 175 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 176 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 177 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 178 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 179 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 180 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 181 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 182 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 183 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 184 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 185 186 187 #endif 188 189 /* #define CONFIG_ID_EEPROM 1 190 #define ID_EEPROM_ADDR 0x57 */ 191 192 /* 193 * The SBC8641D contains 16MB flash space at ff000000. 194 */ 195 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 196 197 /* Flash */ 198 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 199 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 200 201 /* 64KB EEPROM */ 202 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 203 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 204 205 /* EPLD - User switches, board id, LEDs */ 206 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 207 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 208 209 /* Local bus SDRAM 128MB */ 210 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 211 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 212 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 213 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 214 215 /* Disk on Chip (DOC) 128MB */ 216 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 217 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 218 219 /* LCD */ 220 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 221 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 222 223 /* Control logic & misc peripherals */ 224 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 225 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 228 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 229 230 #undef CONFIG_SYS_FLASH_CHECKSUM 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 233 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 234 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 235 236 #define CONFIG_FLASH_CFI_DRIVER 237 #define CONFIG_SYS_FLASH_CFI 238 #define CONFIG_SYS_WRITE_SWAPPED_DATA 239 #define CONFIG_SYS_FLASH_EMPTY_INFO 240 #define CONFIG_SYS_FLASH_PROTECTION 241 242 #undef CONFIG_CLOCKS_IN_MHZ 243 244 #define CONFIG_L1_INIT_RAM 245 #define CONFIG_SYS_INIT_RAM_LOCK 1 246 #ifndef CONFIG_SYS_INIT_RAM_LOCK 247 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 248 #else 249 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 250 #endif 251 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 252 253 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 255 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 256 257 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 258 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 259 260 /* Serial Port */ 261 #define CONFIG_CONS_INDEX 1 262 #undef CONFIG_SERIAL_SOFTWARE_FIFO 263 #define CONFIG_SYS_NS16550 264 #define CONFIG_SYS_NS16550_SERIAL 265 #define CONFIG_SYS_NS16550_REG_SIZE 1 266 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 267 268 #define CONFIG_SYS_BAUDRATE_TABLE \ 269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 270 271 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 272 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 273 274 /* Use the HUSH parser */ 275 #define CONFIG_SYS_HUSH_PARSER 276 #ifdef CONFIG_SYS_HUSH_PARSER 277 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 278 #endif 279 280 /* 281 * Pass open firmware flat tree to kernel 282 */ 283 #define CONFIG_OF_LIBFDT 1 284 #define CONFIG_OF_BOARD_SETUP 1 285 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 286 287 #define CONFIG_SYS_64BIT_VSPRINTF 1 288 #define CONFIG_SYS_64BIT_STRTOUL 1 289 290 /* 291 * I2C 292 */ 293 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 294 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 295 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 296 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 297 #define CONFIG_SYS_I2C_SLAVE 0x7F 298 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 299 #define CONFIG_SYS_I2C_OFFSET 0x3100 300 301 /* 302 * RapidIO MMU 303 */ 304 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ 305 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 306 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 307 308 /* 309 * General PCI 310 * Addresses are mapped 1-1. 311 */ 312 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 313 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 314 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 315 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 316 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 317 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 318 319 #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 320 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 321 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 322 #define CONFIG_SYS_PCI2_IO_BASE 0xe3000000 323 #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BASE 324 #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ 325 326 #if defined(CONFIG_PCI) 327 328 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 329 330 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 331 332 #define CONFIG_NET_MULTI 333 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 334 335 #undef CONFIG_EEPRO100 336 #undef CONFIG_TULIP 337 338 #if !defined(CONFIG_PCI_PNP) 339 #define PCI_ENET0_IOADDR 0xe0000000 340 #define PCI_ENET0_MEMADDR 0xe0000000 341 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 342 #endif 343 344 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 345 346 #define CONFIG_DOS_PARTITION 347 #undef CONFIG_SCSI_AHCI 348 349 #ifdef CONFIG_SCSI_AHCI 350 #define CONFIG_SATA_ULI5288 351 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 352 #define CONFIG_SYS_SCSI_MAX_LUN 1 353 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 354 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 355 #endif 356 357 #endif /* CONFIG_PCI */ 358 359 #if defined(CONFIG_TSEC_ENET) 360 361 #ifndef CONFIG_NET_MULTI 362 #define CONFIG_NET_MULTI 1 363 #endif 364 365 /* #define CONFIG_MII 1 */ /* MII PHY management */ 366 367 #define CONFIG_TSEC1 1 368 #define CONFIG_TSEC1_NAME "eTSEC1" 369 #define CONFIG_TSEC2 1 370 #define CONFIG_TSEC2_NAME "eTSEC2" 371 #define CONFIG_TSEC3 1 372 #define CONFIG_TSEC3_NAME "eTSEC3" 373 #define CONFIG_TSEC4 1 374 #define CONFIG_TSEC4_NAME "eTSEC4" 375 376 #define TSEC1_PHY_ADDR 0x1F 377 #define TSEC2_PHY_ADDR 0x00 378 #define TSEC3_PHY_ADDR 0x01 379 #define TSEC4_PHY_ADDR 0x02 380 #define TSEC1_PHYIDX 0 381 #define TSEC2_PHYIDX 0 382 #define TSEC3_PHYIDX 0 383 #define TSEC4_PHYIDX 0 384 #define TSEC1_FLAGS TSEC_GIGABIT 385 #define TSEC2_FLAGS TSEC_GIGABIT 386 #define TSEC3_FLAGS TSEC_GIGABIT 387 #define TSEC4_FLAGS TSEC_GIGABIT 388 389 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 390 391 #define CONFIG_ETHPRIME "eTSEC1" 392 393 #endif /* CONFIG_TSEC_ENET */ 394 395 /* 396 * BAT0 2G Cacheable, non-guarded 397 * 0x0000_0000 2G DDR 398 */ 399 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 400 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 401 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 402 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 403 404 /* 405 * BAT1 1G Cache-inhibited, guarded 406 * 0x8000_0000 512M PCI-Express 1 Memory 407 * 0xa000_0000 512M PCI-Express 2 Memory 408 * Changed it for operating from 0xd0000000 409 */ 410 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \ 411 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 412 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 413 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 414 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 415 416 /* 417 * BAT2 512M Cache-inhibited, guarded 418 * 0xc000_0000 512M RapidIO Memory 419 */ 420 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ 421 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 422 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 423 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 424 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 425 426 /* 427 * BAT3 4M Cache-inhibited, guarded 428 * 0xf800_0000 4M CCSR 429 */ 430 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 431 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 432 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 433 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 434 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 435 436 /* 437 * BAT4 32M Cache-inhibited, guarded 438 * 0xe200_0000 16M PCI-Express 1 I/O 439 * 0xe300_0000 16M PCI-Express 2 I/0 440 * Note that this is at 0xe0000000 441 */ 442 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \ 443 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 444 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 445 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 446 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 447 448 /* 449 * BAT5 128K Cacheable, non-guarded 450 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 451 */ 452 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 454 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 455 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 456 457 /* 458 * BAT6 32M Cache-inhibited, guarded 459 * 0xfe00_0000 32M FLASH 460 */ 461 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 462 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 463 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 464 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 465 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 466 467 /* Map the last 1M of flash where we're running from reset */ 468 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 469 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 470 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 471 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 472 | BATL_MEMCOHERENCE) 473 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 474 475 #define CONFIG_SYS_DBAT7L 0x00000000 476 #define CONFIG_SYS_DBAT7U 0x00000000 477 #define CONFIG_SYS_IBAT7L 0x00000000 478 #define CONFIG_SYS_IBAT7U 0x00000000 479 480 /* 481 * Environment 482 */ 483 #define CONFIG_ENV_IS_IN_FLASH 1 484 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 485 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 486 #define CONFIG_ENV_SIZE 0x2000 487 488 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 489 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 490 491 #include <config_cmd_default.h> 492 #define CONFIG_CMD_PING 493 #define CONFIG_CMD_I2C 494 #define CONFIG_CMD_REGINFO 495 496 #if defined(CONFIG_PCI) 497 #define CONFIG_CMD_PCI 498 #endif 499 500 #undef CONFIG_WATCHDOG /* watchdog disabled */ 501 502 /* 503 * Miscellaneous configurable options 504 */ 505 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 506 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 507 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 508 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 511 #else 512 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 513 #endif 514 515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 516 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 517 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 518 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 519 520 /* 521 * For booting Linux, the board info and command line data 522 * have to be in the first 8 MB of memory, since this is 523 * the maximum mapped by the Linux kernel during initialization. 524 */ 525 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 526 527 /* Cache Configuration */ 528 #define CONFIG_SYS_DCACHE_SIZE 32768 529 #define CONFIG_SYS_CACHELINE_SIZE 32 530 #if defined(CONFIG_CMD_KGDB) 531 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 532 #endif 533 534 /* 535 * Internal Definitions 536 * 537 * Boot Flags 538 */ 539 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 540 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 541 542 #if defined(CONFIG_CMD_KGDB) 543 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 544 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 545 #endif 546 547 /* 548 * Environment Configuration 549 */ 550 551 /* The mac addresses for all ethernet interface */ 552 #if defined(CONFIG_TSEC_ENET) 553 #define CONFIG_ETHADDR 02:E0:0C:00:00:01 554 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 555 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 556 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 557 #endif 558 559 #define CONFIG_HAS_ETH0 1 560 #define CONFIG_HAS_ETH1 1 561 #define CONFIG_HAS_ETH2 1 562 #define CONFIG_HAS_ETH3 1 563 564 #define CONFIG_IPADDR 192.168.0.50 565 566 #define CONFIG_HOSTNAME sbc8641d 567 #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx 568 #define CONFIG_BOOTFILE uImage 569 570 #define CONFIG_SERVERIP 192.168.0.2 571 #define CONFIG_GATEWAYIP 192.168.0.1 572 #define CONFIG_NETMASK 255.255.255.0 573 574 /* default location for tftp and bootm */ 575 #define CONFIG_LOADADDR 1000000 576 577 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 578 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 579 580 #define CONFIG_BAUDRATE 115200 581 582 #define CONFIG_EXTRA_ENV_SETTINGS \ 583 "netdev=eth0\0" \ 584 "consoledev=ttyS0\0" \ 585 "ramdiskaddr=2000000\0" \ 586 "ramdiskfile=uRamdisk\0" \ 587 "dtbaddr=400000\0" \ 588 "dtbfile=sbc8641d.dtb\0" \ 589 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 590 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 591 "maxcpus=1" 592 593 #define CONFIG_NFSBOOTCOMMAND \ 594 "setenv bootargs root=/dev/nfs rw " \ 595 "nfsroot=$serverip:$rootpath " \ 596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 597 "console=$consoledev,$baudrate $othbootargs;" \ 598 "tftp $loadaddr $bootfile;" \ 599 "tftp $dtbaddr $dtbfile;" \ 600 "bootm $loadaddr - $dtbaddr" 601 602 #define CONFIG_RAMBOOTCOMMAND \ 603 "setenv bootargs root=/dev/ram rw " \ 604 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 605 "console=$consoledev,$baudrate $othbootargs;" \ 606 "tftp $ramdiskaddr $ramdiskfile;" \ 607 "tftp $loadaddr $bootfile;" \ 608 "tftp $dtbaddr $dtbfile;" \ 609 "bootm $loadaddr $ramdiskaddr $dtbaddr" 610 611 #define CONFIG_FLASHBOOTCOMMAND \ 612 "setenv bootargs root=/dev/ram rw " \ 613 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "bootm ffd00000 ffb00000 ffa00000" 616 617 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 618 619 #endif /* __CONFIG_H */ 620