1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * 28 * Please refer to doc/README.sbc85xx for more info. 29 * 30 */ 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 39 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 40 41 #undef CONFIG_PCI /* enable any pci type devices */ 42 #undef CONFIG_PCI1 /* PCI controller 1 */ 43 #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 44 #undef CONFIG_RIO 45 #undef CONFIG_PCI2 46 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 51 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 52 53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 54 55 #define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* toggle branch predition */ 62 63 /* 64 * Only possible on E500 Version 2 or newer cores. 65 */ 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 70 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * Base addresses -- Note these are effective addresses where the 76 * actual resources get mapped (not physical addresses) 77 */ 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 79 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 80 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 81 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 82 83 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 84 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 85 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 86 87 /* DDR Setup */ 88 #define CONFIG_FSL_DDR2 89 #undef CONFIG_FSL_DDR_INTERACTIVE 90 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 91 #undef CONFIG_DDR_SPD 92 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 93 94 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 95 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 96 97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 #define CONFIG_VERY_BIG_RAM 100 101 #define CONFIG_NUM_DDR_CONTROLLERS 1 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 103 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 104 105 /* I2C addresses of SPD EEPROMs */ 106 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 107 108 /* 109 * Make sure required options are set 110 */ 111 #ifndef CONFIG_SPD_EEPROM 112 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 113 #endif 114 115 #undef CONFIG_CLOCKS_IN_MHZ 116 117 /* 118 * FLASH on the Local Bus 119 * Two banks, one 8MB the other 64MB, using the CFI driver. 120 * Boot from BR0/OR0 bank at 0xff80_0000 121 * Alternate BR6/OR6 bank at 0xfb80_0000 122 * 123 * BR0: 124 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 125 * Port Size = 8 bits = BRx[19:20] = 01 126 * Use GPCM = BRx[24:26] = 000 127 * Valid = BRx[31] = 1 128 * 129 * 0 4 8 12 16 20 24 28 130 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 131 * 132 * BR6: 133 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 134 * Port Size = 32 bits = BRx[19:20] = 11 135 * Use GPCM = BRx[24:26] = 000 136 * Valid = BRx[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 140 * 141 * OR0: 142 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 143 * XAM = OR0[17:18] = 11 144 * CSNT = OR0[20] = 1 145 * ACS = half cycle delay = OR0[21:22] = 11 146 * SCY = 6 = OR0[24:27] = 0110 147 * TRLX = use relaxed timing = OR0[29] = 1 148 * EAD = use external address latch delay = OR0[31] = 1 149 * 150 * 0 4 8 12 16 20 24 28 151 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 152 * 153 * OR6: 154 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 155 * XAM = OR6[17:18] = 11 156 * CSNT = OR6[20] = 1 157 * ACS = half cycle delay = OR6[21:22] = 11 158 * SCY = 6 = OR6[24:27] = 0110 159 * TRLX = use relaxed timing = OR6[29] = 1 160 * EAD = use external address latch delay = OR6[31] = 1 161 * 162 * 0 4 8 12 16 20 24 28 163 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 164 */ 165 166 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 167 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 168 169 #define CONFIG_SYS_BR0_PRELIM 0xff800801 170 #define CONFIG_SYS_BR6_PRELIM 0xfb801801 171 172 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 173 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 174 175 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 176 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 178 #undef CONFIG_SYS_FLASH_CHECKSUM 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 188 /* CS5 = Local bus peripherals controlled by the EPLD */ 189 190 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 191 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 192 #define CONFIG_SYS_EPLD_BASE 0xf8000000 193 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 194 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 195 #define CONFIG_SYS_BD_REV 0xf8300000 196 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 197 198 /* 199 * SDRAM on the Local Bus 200 */ 201 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 202 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 203 204 /* 205 * Base Register 3 and Option Register 3 configure SDRAM. 206 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 207 * 208 * For BR3, need: 209 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 210 * port-size = 32-bits = BR2[19:20] = 11 211 * no parity checking = BR2[21:22] = 00 212 * SDRAM for MSEL = BR2[24:26] = 011 213 * Valid = BR[31] = 1 214 * 215 * 0 4 8 12 16 20 24 28 216 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 217 * 218 */ 219 220 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 221 222 /* 223 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 224 * 225 * For OR3, need: 226 * 64MB mask for AM, OR3[0:7] = 1111 1100 227 * XAM, OR3[17:18] = 11 228 * 10 columns OR3[19-21] = 011 229 * 12 rows OR3[23-25] = 011 230 * EAD set for extra time OR[31] = 0 231 * 232 * 0 4 8 12 16 20 24 28 233 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 234 */ 235 236 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 237 238 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 239 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 240 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 241 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 242 243 /* 244 * Common settings for all Local Bus SDRAM commands. 245 * At run time, either BSMA1516 (for CPU 1.1) 246 * or BSMA1617 (for CPU 1.0) (old) 247 * is OR'ed in too. 248 */ 249 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 250 | LSDMR_PRETOACT7 \ 251 | LSDMR_ACTTORW7 \ 252 | LSDMR_BL8 \ 253 | LSDMR_WRC4 \ 254 | LSDMR_CL3 \ 255 | LSDMR_RFEN \ 256 ) 257 258 #define CONFIG_SYS_INIT_RAM_LOCK 1 259 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 260 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 261 262 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 263 264 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 266 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 267 268 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 269 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 270 271 /* Serial Port */ 272 #define CONFIG_CONS_INDEX 1 273 #undef CONFIG_SERIAL_SOFTWARE_FIFO 274 #define CONFIG_SYS_NS16550 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ 278 279 #define CONFIG_SYS_BAUDRATE_TABLE \ 280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 281 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 284 285 /* Use the HUSH parser */ 286 #define CONFIG_SYS_HUSH_PARSER 287 #ifdef CONFIG_SYS_HUSH_PARSER 288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 289 #endif 290 291 /* pass open firmware flat tree */ 292 #define CONFIG_OF_LIBFDT 1 293 #define CONFIG_OF_BOARD_SETUP 1 294 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 295 296 /* 297 * I2C 298 */ 299 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 300 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 301 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 302 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 303 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 304 #define CONFIG_SYS_I2C_SLAVE 0x7F 305 #define CONFIG_SYS_I2C_OFFSET 0x3000 306 307 /* 308 * General PCI 309 * Memory space is mapped 1-1, but I/O space must start from 0. 310 */ 311 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 312 313 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 314 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 315 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 316 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 317 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 318 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 319 320 #ifdef CONFIG_PCI2 321 #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 322 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 323 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 324 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 325 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 326 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 327 #endif 328 329 #ifdef CONFIG_PCIE1 330 #define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 331 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 332 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 333 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 334 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 335 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 336 #endif 337 338 #ifdef CONFIG_RIO 339 /* 340 * RapidIO MMU 341 */ 342 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 343 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 344 #endif 345 346 #ifdef CONFIG_LEGACY 347 #define BRIDGE_ID 17 348 #define VIA_ID 2 349 #else 350 #define BRIDGE_ID 28 351 #define VIA_ID 4 352 #endif 353 354 #if defined(CONFIG_PCI) 355 356 #define CONFIG_NET_MULTI 357 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 358 359 #undef CONFIG_EEPRO100 360 #undef CONFIG_TULIP 361 362 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 363 364 #endif /* CONFIG_PCI */ 365 366 367 #if defined(CONFIG_TSEC_ENET) 368 369 #ifndef CONFIG_NET_MULTI 370 #define CONFIG_NET_MULTI 1 371 #endif 372 373 #define CONFIG_MII 1 /* MII PHY management */ 374 #define CONFIG_TSEC1 1 375 #define CONFIG_TSEC1_NAME "eTSEC0" 376 #define CONFIG_TSEC2 1 377 #define CONFIG_TSEC2_NAME "eTSEC1" 378 #undef CONFIG_MPC85XX_FEC 379 380 #define TSEC1_PHY_ADDR 0x19 381 #define TSEC2_PHY_ADDR 0x1a 382 383 #define TSEC1_PHYIDX 0 384 #define TSEC2_PHYIDX 0 385 386 #define TSEC1_FLAGS TSEC_GIGABIT 387 #define TSEC2_FLAGS TSEC_GIGABIT 388 389 /* Options are: eTSEC[0-3] */ 390 #define CONFIG_ETHPRIME "eTSEC0" 391 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 392 #endif /* CONFIG_TSEC_ENET */ 393 394 /* 395 * Environment 396 */ 397 #define CONFIG_ENV_IS_IN_FLASH 1 398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 399 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 400 #define CONFIG_ENV_SIZE 0x2000 401 402 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 404 405 /* 406 * BOOTP options 407 */ 408 #define CONFIG_BOOTP_BOOTFILESIZE 409 #define CONFIG_BOOTP_BOOTPATH 410 #define CONFIG_BOOTP_GATEWAY 411 #define CONFIG_BOOTP_HOSTNAME 412 413 414 /* 415 * Command line configuration. 416 */ 417 #include <config_cmd_default.h> 418 419 #define CONFIG_CMD_PING 420 #define CONFIG_CMD_I2C 421 #define CONFIG_CMD_MII 422 #define CONFIG_CMD_ELF 423 424 #if defined(CONFIG_PCI) 425 #define CONFIG_CMD_PCI 426 #endif 427 428 429 #undef CONFIG_WATCHDOG /* watchdog disabled */ 430 431 /* 432 * Miscellaneous configurable options 433 */ 434 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 435 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 436 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 437 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 440 #else 441 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 442 #endif 443 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 444 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 445 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 446 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 447 448 /* 449 * For booting Linux, the board info and command line data 450 * have to be in the first 8 MB of memory, since this is 451 * the maximum mapped by the Linux kernel during initialization. 452 */ 453 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 454 455 /* 456 * Internal Definitions 457 * 458 * Boot Flags 459 */ 460 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 461 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 462 463 #if defined(CONFIG_CMD_KGDB) 464 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 465 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 466 #endif 467 468 /* 469 * Environment Configuration 470 */ 471 472 /* The mac addresses for all ethernet interface */ 473 #if defined(CONFIG_TSEC_ENET) 474 #define CONFIG_HAS_ETH0 475 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 476 #define CONFIG_HAS_ETH1 477 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 478 #endif 479 480 #define CONFIG_IPADDR 192.168.0.55 481 482 #define CONFIG_HOSTNAME sbc8548 483 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 484 #define CONFIG_BOOTFILE /uImage 485 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 486 487 #define CONFIG_SERVERIP 192.168.0.2 488 #define CONFIG_GATEWAYIP 192.168.0.1 489 #define CONFIG_NETMASK 255.255.255.0 490 491 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 492 493 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 494 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 495 496 #define CONFIG_BAUDRATE 115200 497 498 #define CONFIG_EXTRA_ENV_SETTINGS \ 499 "netdev=eth0\0" \ 500 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 501 "tftpflash=tftpboot $loadaddr $uboot; " \ 502 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 503 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 504 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 505 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 506 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 507 "consoledev=ttyS0\0" \ 508 "ramdiskaddr=2000000\0" \ 509 "ramdiskfile=uRamdisk\0" \ 510 "fdtaddr=c00000\0" \ 511 "fdtfile=sbc8548.dtb\0" 512 513 #define CONFIG_NFSBOOTCOMMAND \ 514 "setenv bootargs root=/dev/nfs rw " \ 515 "nfsroot=$serverip:$rootpath " \ 516 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 517 "console=$consoledev,$baudrate $othbootargs;" \ 518 "tftp $loadaddr $bootfile;" \ 519 "tftp $fdtaddr $fdtfile;" \ 520 "bootm $loadaddr - $fdtaddr" 521 522 523 #define CONFIG_RAMBOOTCOMMAND \ 524 "setenv bootargs root=/dev/ram rw " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $ramdiskaddr $ramdiskfile;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr $ramdiskaddr $fdtaddr" 530 531 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 532 533 #endif /* __CONFIG_H */ 534