1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * Top level Makefile configuration choices 18 */ 19 #ifdef CONFIG_PCI 20 #define CONFIG_PCI_INDIRECT_BRIDGE 21 #define CONFIG_PCI1 22 #endif 23 24 #ifdef CONFIG_66 25 #define CONFIG_SYS_CLK_DIV 1 26 #endif 27 28 #ifdef CONFIG_33 29 #define CONFIG_SYS_CLK_DIV 2 30 #endif 31 32 #ifdef CONFIG_PCIE 33 #define CONFIG_PCIE1 34 #endif 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 40 41 /* 42 * If you want to boot from the SODIMM flash, instead of the soldered 43 * on flash, set this, and change JP12, SW2:8 accordingly. 44 */ 45 #undef CONFIG_SYS_ALT_BOOT 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #ifdef CONFIG_SYS_ALT_BOOT 49 #define CONFIG_SYS_TEXT_BASE 0xfff00000 50 #else 51 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 52 #endif 53 #endif 54 55 #undef CONFIG_RIO 56 57 #ifdef CONFIG_PCI 58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 59 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 60 #endif 61 #ifdef CONFIG_PCIE1 62 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 63 #endif 64 65 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 66 #define CONFIG_ENV_OVERWRITE 67 68 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 69 70 /* 71 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 72 */ 73 #ifndef CONFIG_SYS_CLK_DIV 74 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 75 #endif 76 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 77 78 /* 79 * These can be toggled for performance analysis, otherwise use default. 80 */ 81 #define CONFIG_L2_CACHE /* toggle L2 cache */ 82 #define CONFIG_BTB /* toggle branch predition */ 83 84 /* 85 * Only possible on E500 Version 2 or newer cores. 86 */ 87 #define CONFIG_ENABLE_36BIT_PHYS 1 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 91 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 95 #define CONFIG_SYS_CCSRBAR 0xe0000000 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 98 /* DDR Setup */ 99 #define CONFIG_SYS_FSL_DDR2 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 102 /* 103 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 104 * to collide, meaning you couldn't reliably read either. So 105 * physically remove the LBC PC100 SDRAM module from the board 106 * before enabling the two SPD options below, or check that you 107 * have the hardware fix on your board via "i2c probe" and looking 108 * for a device at 0x53. 109 */ 110 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 111 #undef CONFIG_DDR_SPD 112 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 #define CONFIG_VERY_BIG_RAM 119 120 #define CONFIG_NUM_DDR_CONTROLLERS 1 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 123 124 /* 125 * The hardware fix for the I2C address collision puts the DDR 126 * SPD at 0x53, but if we are running on an older board w/o the 127 * fix, it will still be at 0x51. We check 0x53 1st. 128 */ 129 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 130 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 131 132 /* 133 * Make sure required options are set 134 */ 135 #ifndef CONFIG_SPD_EEPROM 136 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 137 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 138 #endif 139 140 #undef CONFIG_CLOCKS_IN_MHZ 141 142 /* 143 * FLASH on the Local Bus 144 * Two banks, one 8MB the other 64MB, using the CFI driver. 145 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 146 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 147 * 148 * Default: 149 * ec00_0000 efff_ffff 64MB SODIMM 150 * ff80_0000 ffff_ffff 8MB soldered flash 151 * 152 * Alternate: 153 * ef80_0000 efff_ffff 8MB soldered flash 154 * fc00_0000 ffff_ffff 64MB SODIMM 155 * 156 * BR0_8M: 157 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 158 * Port Size = 8 bits = BRx[19:20] = 01 159 * Use GPCM = BRx[24:26] = 000 160 * Valid = BRx[31] = 1 161 * 162 * BR0_64M: 163 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 164 * Port Size = 32 bits = BRx[19:20] = 11 165 * 166 * 0 4 8 12 16 20 24 28 167 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 168 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 169 */ 170 #define CONFIG_SYS_BR0_8M 0xff800801 171 #define CONFIG_SYS_BR0_64M 0xfc001801 172 173 /* 174 * BR6_8M: 175 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 176 * Port Size = 8 bits = BRx[19:20] = 01 177 * Use GPCM = BRx[24:26] = 000 178 * Valid = BRx[31] = 1 179 180 * BR6_64M: 181 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 182 * Port Size = 32 bits = BRx[19:20] = 11 183 * 184 * 0 4 8 12 16 20 24 28 185 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 186 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 187 */ 188 #define CONFIG_SYS_BR6_8M 0xef800801 189 #define CONFIG_SYS_BR6_64M 0xec001801 190 191 /* 192 * OR0_8M: 193 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 194 * XAM = OR0[17:18] = 11 195 * CSNT = OR0[20] = 1 196 * ACS = half cycle delay = OR0[21:22] = 11 197 * SCY = 6 = OR0[24:27] = 0110 198 * TRLX = use relaxed timing = OR0[29] = 1 199 * EAD = use external address latch delay = OR0[31] = 1 200 * 201 * OR0_64M: 202 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 203 * 204 * 205 * 0 4 8 12 16 20 24 28 206 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 207 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 208 */ 209 #define CONFIG_SYS_OR0_8M 0xff806e65 210 #define CONFIG_SYS_OR0_64M 0xfc006e65 211 212 /* 213 * OR6_8M: 214 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 215 * XAM = OR6[17:18] = 11 216 * CSNT = OR6[20] = 1 217 * ACS = half cycle delay = OR6[21:22] = 11 218 * SCY = 6 = OR6[24:27] = 0110 219 * TRLX = use relaxed timing = OR6[29] = 1 220 * EAD = use external address latch delay = OR6[31] = 1 221 * 222 * OR6_64M: 223 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 224 * 225 * 0 4 8 12 16 20 24 28 226 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 227 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 228 */ 229 #define CONFIG_SYS_OR6_8M 0xff806e65 230 #define CONFIG_SYS_OR6_64M 0xfc006e65 231 232 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 233 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 234 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 235 236 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 237 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 238 239 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 240 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 241 #else /* JP12 in alternate position */ 242 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 243 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 244 245 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 246 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 247 248 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 249 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 250 #endif 251 252 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 253 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 254 CONFIG_SYS_ALT_FLASH} 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 256 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 257 #undef CONFIG_SYS_FLASH_CHECKSUM 258 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 259 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 260 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 262 263 #define CONFIG_FLASH_CFI_DRIVER 264 #define CONFIG_SYS_FLASH_CFI 265 #define CONFIG_SYS_FLASH_EMPTY_INFO 266 267 /* CS5 = Local bus peripherals controlled by the EPLD */ 268 269 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 270 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 271 #define CONFIG_SYS_EPLD_BASE 0xf8000000 272 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 273 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 274 #define CONFIG_SYS_BD_REV 0xf8300000 275 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 276 277 /* 278 * SDRAM on the Local Bus (CS3 and CS4) 279 * Note that most boards have a hardware errata where both the 280 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 281 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 282 * A hardware workaround is also available, see README.sbc8548 file. 283 */ 284 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 285 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 286 287 /* 288 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 289 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 290 * 291 * For BR3, need: 292 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 293 * port-size = 32-bits = BR2[19:20] = 11 294 * no parity checking = BR2[21:22] = 00 295 * SDRAM for MSEL = BR2[24:26] = 011 296 * Valid = BR[31] = 1 297 * 298 * 0 4 8 12 16 20 24 28 299 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 300 * 301 */ 302 303 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 304 305 /* 306 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 307 * 308 * For OR3, need: 309 * 64MB mask for AM, OR3[0:7] = 1111 1100 310 * XAM, OR3[17:18] = 11 311 * 10 columns OR3[19-21] = 011 312 * 12 rows OR3[23-25] = 011 313 * EAD set for extra time OR[31] = 0 314 * 315 * 0 4 8 12 16 20 24 28 316 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 317 */ 318 319 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 320 321 /* 322 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 323 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 324 * 325 * For BR4, need: 326 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 327 * port-size = 32-bits = BR2[19:20] = 11 328 * no parity checking = BR2[21:22] = 00 329 * SDRAM for MSEL = BR2[24:26] = 011 330 * Valid = BR[31] = 1 331 * 332 * 0 4 8 12 16 20 24 28 333 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 334 * 335 */ 336 337 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 338 339 /* 340 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 341 * 342 * For OR4, need: 343 * 64MB mask for AM, OR3[0:7] = 1111 1100 344 * XAM, OR3[17:18] = 11 345 * 10 columns OR3[19-21] = 011 346 * 12 rows OR3[23-25] = 011 347 * EAD set for extra time OR[31] = 0 348 * 349 * 0 4 8 12 16 20 24 28 350 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 351 */ 352 353 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 354 355 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 356 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 357 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 358 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 359 360 /* 361 * Common settings for all Local Bus SDRAM commands. 362 */ 363 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 364 | LSDMR_BSMA1516 \ 365 | LSDMR_PRETOACT3 \ 366 | LSDMR_ACTTORW3 \ 367 | LSDMR_BUFCMD \ 368 | LSDMR_BL8 \ 369 | LSDMR_WRC2 \ 370 | LSDMR_CL3 \ 371 ) 372 373 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 374 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 375 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 376 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 377 #define CONFIG_SYS_LBC_LSDMR_MRW \ 378 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 379 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 380 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 381 382 #define CONFIG_SYS_INIT_RAM_LOCK 1 383 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 384 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 385 386 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 387 388 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 389 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 390 391 /* 392 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 393 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 394 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 395 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 396 * thing for MONITOR_LEN in both cases. 397 */ 398 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 399 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 400 401 /* Serial Port */ 402 #define CONFIG_CONS_INDEX 1 403 #define CONFIG_SYS_NS16550_SERIAL 404 #define CONFIG_SYS_NS16550_REG_SIZE 1 405 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 406 407 #define CONFIG_SYS_BAUDRATE_TABLE \ 408 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 409 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 412 413 /* 414 * I2C 415 */ 416 #define CONFIG_SYS_I2C 417 #define CONFIG_SYS_I2C_FSL 418 #define CONFIG_SYS_FSL_I2C_SPEED 400000 419 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 421 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 422 423 /* 424 * General PCI 425 * Memory space is mapped 1-1, but I/O space must start from 0. 426 */ 427 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 428 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 429 430 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 431 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 432 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 433 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 435 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 436 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 437 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 438 439 #ifdef CONFIG_PCIE1 440 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 441 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 442 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 443 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 444 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 445 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 447 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 448 #endif 449 450 #ifdef CONFIG_RIO 451 /* 452 * RapidIO MMU 453 */ 454 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 455 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 456 #endif 457 458 #if defined(CONFIG_PCI) 459 #undef CONFIG_EEPRO100 460 #undef CONFIG_TULIP 461 462 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 463 464 #endif /* CONFIG_PCI */ 465 466 #if defined(CONFIG_TSEC_ENET) 467 468 #define CONFIG_MII 1 /* MII PHY management */ 469 #define CONFIG_TSEC1 1 470 #define CONFIG_TSEC1_NAME "eTSEC0" 471 #define CONFIG_TSEC2 1 472 #define CONFIG_TSEC2_NAME "eTSEC1" 473 #undef CONFIG_MPC85XX_FEC 474 475 #define TSEC1_PHY_ADDR 0x19 476 #define TSEC2_PHY_ADDR 0x1a 477 478 #define TSEC1_PHYIDX 0 479 #define TSEC2_PHYIDX 0 480 481 #define TSEC1_FLAGS TSEC_GIGABIT 482 #define TSEC2_FLAGS TSEC_GIGABIT 483 484 /* Options are: eTSEC[0-3] */ 485 #define CONFIG_ETHPRIME "eTSEC0" 486 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 487 #endif /* CONFIG_TSEC_ENET */ 488 489 /* 490 * Environment 491 */ 492 #define CONFIG_ENV_IS_IN_FLASH 1 493 #define CONFIG_ENV_SIZE 0x2000 494 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 496 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 497 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 498 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 499 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 500 #else 501 #warning undefined environment size/location. 502 #endif 503 504 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 505 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 506 507 /* 508 * BOOTP options 509 */ 510 #define CONFIG_BOOTP_BOOTFILESIZE 511 #define CONFIG_BOOTP_BOOTPATH 512 #define CONFIG_BOOTP_GATEWAY 513 #define CONFIG_BOOTP_HOSTNAME 514 515 /* 516 * Command line configuration. 517 */ 518 #define CONFIG_CMD_REGINFO 519 520 #if defined(CONFIG_PCI) 521 #define CONFIG_CMD_PCI 522 #endif 523 524 #undef CONFIG_WATCHDOG /* watchdog disabled */ 525 526 /* 527 * Miscellaneous configurable options 528 */ 529 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 530 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 531 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 532 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 533 #if defined(CONFIG_CMD_KGDB) 534 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 535 #else 536 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 537 #endif 538 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 539 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 540 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 541 542 /* 543 * For booting Linux, the board info and command line data 544 * have to be in the first 8 MB of memory, since this is 545 * the maximum mapped by the Linux kernel during initialization. 546 */ 547 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 548 549 #if defined(CONFIG_CMD_KGDB) 550 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 551 #endif 552 553 /* 554 * Environment Configuration 555 */ 556 #if defined(CONFIG_TSEC_ENET) 557 #define CONFIG_HAS_ETH0 558 #define CONFIG_HAS_ETH1 559 #endif 560 561 #define CONFIG_IPADDR 192.168.0.55 562 563 #define CONFIG_HOSTNAME sbc8548 564 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 565 #define CONFIG_BOOTFILE "/uImage" 566 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 567 568 #define CONFIG_SERVERIP 192.168.0.2 569 #define CONFIG_GATEWAYIP 192.168.0.1 570 #define CONFIG_NETMASK 255.255.255.0 571 572 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 573 574 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 575 576 #define CONFIG_BAUDRATE 115200 577 578 #define CONFIG_EXTRA_ENV_SETTINGS \ 579 "netdev=eth0\0" \ 580 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 581 "tftpflash=tftpboot $loadaddr $uboot; " \ 582 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 583 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 584 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 585 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 586 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 587 "consoledev=ttyS0\0" \ 588 "ramdiskaddr=2000000\0" \ 589 "ramdiskfile=uRamdisk\0" \ 590 "fdtaddr=1e00000\0" \ 591 "fdtfile=sbc8548.dtb\0" 592 593 #define CONFIG_NFSBOOTCOMMAND \ 594 "setenv bootargs root=/dev/nfs rw " \ 595 "nfsroot=$serverip:$rootpath " \ 596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 597 "console=$consoledev,$baudrate $othbootargs;" \ 598 "tftp $loadaddr $bootfile;" \ 599 "tftp $fdtaddr $fdtfile;" \ 600 "bootm $loadaddr - $fdtaddr" 601 602 #define CONFIG_RAMBOOTCOMMAND \ 603 "setenv bootargs root=/dev/ram rw " \ 604 "console=$consoledev,$baudrate $othbootargs;" \ 605 "tftp $ramdiskaddr $ramdiskfile;" \ 606 "tftp $loadaddr $bootfile;" \ 607 "tftp $fdtaddr $fdtfile;" \ 608 "bootm $loadaddr $ramdiskaddr $fdtaddr" 609 610 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 611 612 #endif /* __CONFIG_H */ 613