1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * Please refer to doc/README.sbc8548 for more info. 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * Top level Makefile configuration choices 34 */ 35 #ifdef CONFIG_PCI 36 #define CONFIG_PCI1 37 #endif 38 39 #ifdef CONFIG_66 40 #define CONFIG_SYS_CLK_DIV 1 41 #endif 42 43 #ifdef CONFIG_33 44 #define CONFIG_SYS_CLK_DIV 2 45 #endif 46 47 #ifdef CONFIG_PCIE 48 #define CONFIG_PCIE1 49 #endif 50 51 /* 52 * High Level Configuration Options 53 */ 54 #define CONFIG_BOOKE 1 /* BOOKE */ 55 #define CONFIG_E500 1 /* BOOKE e500 family */ 56 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 57 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 58 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 59 60 /* 61 * If you want to boot from the SODIMM flash, instead of the soldered 62 * on flash, set this, and change JP12, SW2:8 accordingly. 63 */ 64 #undef CONFIG_SYS_ALT_BOOT 65 66 #ifndef CONFIG_SYS_TEXT_BASE 67 #ifdef CONFIG_SYS_ALT_BOOT 68 #define CONFIG_SYS_TEXT_BASE 0xfff00000 69 #else 70 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 71 #endif 72 #endif 73 74 #undef CONFIG_RIO 75 76 #ifdef CONFIG_PCI 77 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 78 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 79 #endif 80 #ifdef CONFIG_PCIE1 81 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 82 #endif 83 84 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 85 #define CONFIG_ENV_OVERWRITE 86 87 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 88 89 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 90 91 /* 92 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 93 */ 94 #ifndef CONFIG_SYS_CLK_DIV 95 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 96 #endif 97 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 98 99 /* 100 * These can be toggled for performance analysis, otherwise use default. 101 */ 102 #define CONFIG_L2_CACHE /* toggle L2 cache */ 103 #define CONFIG_BTB /* toggle branch predition */ 104 105 /* 106 * Only possible on E500 Version 2 or newer cores. 107 */ 108 #define CONFIG_ENABLE_36BIT_PHYS 1 109 110 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 111 112 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 113 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 114 #define CONFIG_SYS_MEMTEST_END 0x00400000 115 116 #define CONFIG_SYS_CCSRBAR 0xe0000000 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 118 119 /* DDR Setup */ 120 #define CONFIG_FSL_DDR2 121 #undef CONFIG_FSL_DDR_INTERACTIVE 122 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 123 /* 124 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 125 * to collide, meaning you couldn't reliably read either. So 126 * physically remove the LBC PC100 SDRAM module from the board 127 * before enabling the two SPD options below. 128 */ 129 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 130 #undef CONFIG_DDR_SPD 131 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 133 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 134 135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 137 #define CONFIG_VERY_BIG_RAM 138 139 #define CONFIG_NUM_DDR_CONTROLLERS 1 140 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 141 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 142 143 /* I2C addresses of SPD EEPROMs */ 144 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 145 146 /* 147 * Make sure required options are set 148 */ 149 #ifndef CONFIG_SPD_EEPROM 150 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 151 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 152 #endif 153 154 #undef CONFIG_CLOCKS_IN_MHZ 155 156 /* 157 * FLASH on the Local Bus 158 * Two banks, one 8MB the other 64MB, using the CFI driver. 159 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 160 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 161 * 162 * Default: 163 * ec00_0000 efff_ffff 64MB SODIMM 164 * ff80_0000 ffff_ffff 8MB soldered flash 165 * 166 * Alternate: 167 * ef80_0000 efff_ffff 8MB soldered flash 168 * fc00_0000 ffff_ffff 64MB SODIMM 169 * 170 * BR0_8M: 171 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 172 * Port Size = 8 bits = BRx[19:20] = 01 173 * Use GPCM = BRx[24:26] = 000 174 * Valid = BRx[31] = 1 175 * 176 * BR0_64M: 177 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 178 * Port Size = 32 bits = BRx[19:20] = 11 179 * 180 * 0 4 8 12 16 20 24 28 181 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 182 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 183 */ 184 #define CONFIG_SYS_BR0_8M 0xff800801 185 #define CONFIG_SYS_BR0_64M 0xfc001801 186 187 /* 188 * BR6_8M: 189 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 190 * Port Size = 8 bits = BRx[19:20] = 01 191 * Use GPCM = BRx[24:26] = 000 192 * Valid = BRx[31] = 1 193 194 * BR6_64M: 195 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 196 * Port Size = 32 bits = BRx[19:20] = 11 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 200 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 201 */ 202 #define CONFIG_SYS_BR6_8M 0xef800801 203 #define CONFIG_SYS_BR6_64M 0xec001801 204 205 /* 206 * OR0_8M: 207 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 208 * XAM = OR0[17:18] = 11 209 * CSNT = OR0[20] = 1 210 * ACS = half cycle delay = OR0[21:22] = 11 211 * SCY = 6 = OR0[24:27] = 0110 212 * TRLX = use relaxed timing = OR0[29] = 1 213 * EAD = use external address latch delay = OR0[31] = 1 214 * 215 * OR0_64M: 216 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 217 * 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 221 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 222 */ 223 #define CONFIG_SYS_OR0_8M 0xff806e65 224 #define CONFIG_SYS_OR0_64M 0xfc006e65 225 226 /* 227 * OR6_8M: 228 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 229 * XAM = OR6[17:18] = 11 230 * CSNT = OR6[20] = 1 231 * ACS = half cycle delay = OR6[21:22] = 11 232 * SCY = 6 = OR6[24:27] = 0110 233 * TRLX = use relaxed timing = OR6[29] = 1 234 * EAD = use external address latch delay = OR6[31] = 1 235 * 236 * OR6_64M: 237 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 238 * 239 * 0 4 8 12 16 20 24 28 240 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 241 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 242 */ 243 #define CONFIG_SYS_OR6_8M 0xff806e65 244 #define CONFIG_SYS_OR6_64M 0xfc006e65 245 246 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 247 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 248 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 249 250 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 251 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 252 253 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 254 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 255 #else /* JP12 in alternate position */ 256 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 257 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 258 259 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 260 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 261 262 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 263 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 264 #endif 265 266 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 268 CONFIG_SYS_ALT_FLASH} 269 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 270 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 271 #undef CONFIG_SYS_FLASH_CHECKSUM 272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 274 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 276 277 #define CONFIG_FLASH_CFI_DRIVER 278 #define CONFIG_SYS_FLASH_CFI 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 281 /* CS5 = Local bus peripherals controlled by the EPLD */ 282 283 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 284 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 285 #define CONFIG_SYS_EPLD_BASE 0xf8000000 286 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 287 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 288 #define CONFIG_SYS_BD_REV 0xf8300000 289 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 290 291 /* 292 * SDRAM on the Local Bus (CS3 and CS4) 293 * Note that most boards have a hardware errata where both the 294 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 295 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 296 */ 297 #ifndef CONFIG_DDR_SPD 298 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 299 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 300 #endif 301 302 /* 303 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 304 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 305 * 306 * For BR3, need: 307 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 308 * port-size = 32-bits = BR2[19:20] = 11 309 * no parity checking = BR2[21:22] = 00 310 * SDRAM for MSEL = BR2[24:26] = 011 311 * Valid = BR[31] = 1 312 * 313 * 0 4 8 12 16 20 24 28 314 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 315 * 316 */ 317 318 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 319 320 /* 321 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 322 * 323 * For OR3, need: 324 * 64MB mask for AM, OR3[0:7] = 1111 1100 325 * XAM, OR3[17:18] = 11 326 * 10 columns OR3[19-21] = 011 327 * 12 rows OR3[23-25] = 011 328 * EAD set for extra time OR[31] = 0 329 * 330 * 0 4 8 12 16 20 24 28 331 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 332 */ 333 334 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 335 336 /* 337 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 338 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 339 * 340 * For BR4, need: 341 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 342 * port-size = 32-bits = BR2[19:20] = 11 343 * no parity checking = BR2[21:22] = 00 344 * SDRAM for MSEL = BR2[24:26] = 011 345 * Valid = BR[31] = 1 346 * 347 * 0 4 8 12 16 20 24 28 348 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 349 * 350 */ 351 352 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 353 354 /* 355 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 356 * 357 * For OR4, need: 358 * 64MB mask for AM, OR3[0:7] = 1111 1100 359 * XAM, OR3[17:18] = 11 360 * 10 columns OR3[19-21] = 011 361 * 12 rows OR3[23-25] = 011 362 * EAD set for extra time OR[31] = 0 363 * 364 * 0 4 8 12 16 20 24 28 365 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 366 */ 367 368 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 369 370 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 371 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 372 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 373 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 374 375 /* 376 * Common settings for all Local Bus SDRAM commands. 377 */ 378 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 379 | LSDMR_BSMA1516 \ 380 | LSDMR_PRETOACT3 \ 381 | LSDMR_ACTTORW3 \ 382 | LSDMR_BUFCMD \ 383 | LSDMR_BL8 \ 384 | LSDMR_WRC2 \ 385 | LSDMR_CL3 \ 386 ) 387 388 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 389 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 390 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 391 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 392 #define CONFIG_SYS_LBC_LSDMR_MRW \ 393 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 394 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 395 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 396 397 #define CONFIG_SYS_INIT_RAM_LOCK 1 398 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 399 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 400 401 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 402 403 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 404 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 405 406 /* 407 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 408 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 409 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 410 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 411 * thing for MONITOR_LEN in both cases. 412 */ 413 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 414 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 415 416 /* Serial Port */ 417 #define CONFIG_CONS_INDEX 1 418 #define CONFIG_SYS_NS16550 419 #define CONFIG_SYS_NS16550_SERIAL 420 #define CONFIG_SYS_NS16550_REG_SIZE 1 421 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 422 423 #define CONFIG_SYS_BAUDRATE_TABLE \ 424 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 425 426 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 427 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 428 429 /* Use the HUSH parser */ 430 #define CONFIG_SYS_HUSH_PARSER 431 #ifdef CONFIG_SYS_HUSH_PARSER 432 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 433 #endif 434 435 /* pass open firmware flat tree */ 436 #define CONFIG_OF_LIBFDT 1 437 #define CONFIG_OF_BOARD_SETUP 1 438 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 439 440 /* 441 * I2C 442 */ 443 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 444 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 445 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 446 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 447 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 448 #define CONFIG_SYS_I2C_SLAVE 0x7F 449 #define CONFIG_SYS_I2C_OFFSET 0x3000 450 451 /* 452 * General PCI 453 * Memory space is mapped 1-1, but I/O space must start from 0. 454 */ 455 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 456 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 457 458 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 459 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 460 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 461 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 462 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 463 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 464 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 465 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 466 467 #ifdef CONFIG_PCIE1 468 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 469 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 470 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 471 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 473 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 474 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 475 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 476 #endif 477 478 #ifdef CONFIG_RIO 479 /* 480 * RapidIO MMU 481 */ 482 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 483 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 484 #endif 485 486 #if defined(CONFIG_PCI) 487 488 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 489 490 #undef CONFIG_EEPRO100 491 #undef CONFIG_TULIP 492 493 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 494 495 #endif /* CONFIG_PCI */ 496 497 498 #if defined(CONFIG_TSEC_ENET) 499 500 #define CONFIG_MII 1 /* MII PHY management */ 501 #define CONFIG_TSEC1 1 502 #define CONFIG_TSEC1_NAME "eTSEC0" 503 #define CONFIG_TSEC2 1 504 #define CONFIG_TSEC2_NAME "eTSEC1" 505 #undef CONFIG_MPC85XX_FEC 506 507 #define TSEC1_PHY_ADDR 0x19 508 #define TSEC2_PHY_ADDR 0x1a 509 510 #define TSEC1_PHYIDX 0 511 #define TSEC2_PHYIDX 0 512 513 #define TSEC1_FLAGS TSEC_GIGABIT 514 #define TSEC2_FLAGS TSEC_GIGABIT 515 516 /* Options are: eTSEC[0-3] */ 517 #define CONFIG_ETHPRIME "eTSEC0" 518 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 519 #endif /* CONFIG_TSEC_ENET */ 520 521 /* 522 * Environment 523 */ 524 #define CONFIG_ENV_IS_IN_FLASH 1 525 #define CONFIG_ENV_SIZE 0x2000 526 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 527 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 528 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 529 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 530 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 531 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 532 #else 533 #warning undefined environment size/location. 534 #endif 535 536 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 537 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 538 539 /* 540 * BOOTP options 541 */ 542 #define CONFIG_BOOTP_BOOTFILESIZE 543 #define CONFIG_BOOTP_BOOTPATH 544 #define CONFIG_BOOTP_GATEWAY 545 #define CONFIG_BOOTP_HOSTNAME 546 547 548 /* 549 * Command line configuration. 550 */ 551 #include <config_cmd_default.h> 552 553 #define CONFIG_CMD_PING 554 #define CONFIG_CMD_I2C 555 #define CONFIG_CMD_MII 556 #define CONFIG_CMD_ELF 557 #define CONFIG_CMD_REGINFO 558 559 #if defined(CONFIG_PCI) 560 #define CONFIG_CMD_PCI 561 #endif 562 563 564 #undef CONFIG_WATCHDOG /* watchdog disabled */ 565 566 /* 567 * Miscellaneous configurable options 568 */ 569 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 570 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 571 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 572 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 573 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 574 #if defined(CONFIG_CMD_KGDB) 575 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 576 #else 577 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 578 #endif 579 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 580 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 581 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 582 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 583 584 /* 585 * For booting Linux, the board info and command line data 586 * have to be in the first 8 MB of memory, since this is 587 * the maximum mapped by the Linux kernel during initialization. 588 */ 589 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 590 591 #if defined(CONFIG_CMD_KGDB) 592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 593 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 594 #endif 595 596 /* 597 * Environment Configuration 598 */ 599 600 /* The mac addresses for all ethernet interface */ 601 #if defined(CONFIG_TSEC_ENET) 602 #define CONFIG_HAS_ETH0 603 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 604 #define CONFIG_HAS_ETH1 605 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 606 #endif 607 608 #define CONFIG_IPADDR 192.168.0.55 609 610 #define CONFIG_HOSTNAME sbc8548 611 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 612 #define CONFIG_BOOTFILE "/uImage" 613 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 614 615 #define CONFIG_SERVERIP 192.168.0.2 616 #define CONFIG_GATEWAYIP 192.168.0.1 617 #define CONFIG_NETMASK 255.255.255.0 618 619 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 620 621 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 622 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 623 624 #define CONFIG_BAUDRATE 115200 625 626 #define CONFIG_EXTRA_ENV_SETTINGS \ 627 "netdev=eth0\0" \ 628 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 629 "tftpflash=tftpboot $loadaddr $uboot; " \ 630 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 631 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 632 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 633 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 634 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 635 "consoledev=ttyS0\0" \ 636 "ramdiskaddr=2000000\0" \ 637 "ramdiskfile=uRamdisk\0" \ 638 "fdtaddr=c00000\0" \ 639 "fdtfile=sbc8548.dtb\0" 640 641 #define CONFIG_NFSBOOTCOMMAND \ 642 "setenv bootargs root=/dev/nfs rw " \ 643 "nfsroot=$serverip:$rootpath " \ 644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 645 "console=$consoledev,$baudrate $othbootargs;" \ 646 "tftp $loadaddr $bootfile;" \ 647 "tftp $fdtaddr $fdtfile;" \ 648 "bootm $loadaddr - $fdtaddr" 649 650 651 #define CONFIG_RAMBOOTCOMMAND \ 652 "setenv bootargs root=/dev/ram rw " \ 653 "console=$consoledev,$baudrate $othbootargs;" \ 654 "tftp $ramdiskaddr $ramdiskfile;" \ 655 "tftp $loadaddr $bootfile;" \ 656 "tftp $fdtaddr $fdtfile;" \ 657 "bootm $loadaddr $ramdiskaddr $fdtaddr" 658 659 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 660 661 #endif /* __CONFIG_H */ 662