1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 39 #define CONFIG_MPC834x 1 /* MPC834x family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 42 43 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 44 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 45 46 /* 47 * The default if PCI isn't enabled, or if no PCI clk setting is given 48 * is 66MHz; this is what the board defaults to when the PCI slot is 49 * physically empty. The board will automatically (i.e w/o jumpers) 50 * clock down to 33MHz if you insert a 33MHz PCI card. 51 */ 52 #ifdef PCI_33M 53 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 54 #else /* 66M */ 55 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 56 #endif 57 58 #ifndef CONFIG_SYS_CLK_FREQ 59 #ifdef PCI_33M 60 #define CONFIG_SYS_CLK_FREQ 33000000 61 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 62 #else /* 66M */ 63 #define CONFIG_SYS_CLK_FREQ 66000000 64 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 65 #endif 66 #endif 67 68 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 69 70 #define CONFIG_SYS_IMMR 0xE0000000 71 72 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 73 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00100000 75 76 /* 77 * DDR Setup 78 */ 79 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 80 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 81 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 82 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 83 84 /* 85 * 32-bit data path mode. 86 * 87 * Please note that using this mode for devices with the real density of 64-bit 88 * effectively reduces the amount of available memory due to the effect of 89 * wrapping around while translating address to row/columns, for example in the 90 * 256MB module the upper 128MB get aliased with contents of the lower 91 * 128MB); normally this define should be used for devices with real 32-bit 92 * data path. 93 */ 94 #undef CONFIG_DDR_32BIT 95 96 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 98 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 99 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 100 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 101 #define CONFIG_DDR_2T_TIMING 102 103 #if defined(CONFIG_SPD_EEPROM) 104 /* 105 * Determine DDR configuration from I2C interface. 106 */ 107 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 108 109 #else 110 /* 111 * Manually set up DDR parameters 112 * NB: manual DDR setup untested on sbc834x 113 */ 114 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 115 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 116 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 117 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 118 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 119 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 120 121 #if defined(CONFIG_DDR_32BIT) 122 /* set burst length to 8 for 32-bit data path */ 123 #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 124 #else 125 /* the default burst length is 4 - for 64-bit data path */ 126 #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 127 #endif 128 #endif 129 130 /* 131 * SDRAM on the Local Bus 132 */ 133 #define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 134 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 135 136 /* 137 * FLASH on the Local Bus 138 */ 139 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 140 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 141 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 142 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 143 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 144 145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 146 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 147 BR_V) /* valid */ 148 149 #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 150 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 151 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 152 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 155 156 #undef CONFIG_SYS_FLASH_CHECKSUM 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000 161 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 162 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 164 #define CONFIG_SYS_RAMBOOT 165 #else 166 #undef CONFIG_SYS_RAMBOOT 167 #endif 168 169 #define CONFIG_SYS_INIT_RAM_LOCK 1 170 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 171 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 172 173 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 177 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 178 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 179 180 /* 181 * Local Bus LCRR and LBCR regs 182 * LCRR: DLL bypass, Clock divider is 4 183 * External Local Bus rate is 184 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 185 */ 186 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 187 #define CONFIG_SYS_LBC_LBCR 0x00000000 188 189 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 190 191 #ifdef CONFIG_SYS_LB_SDRAM 192 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 193 /* 194 * Base Register 2 and Option Register 2 configure SDRAM. 195 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 196 * 197 * For BR2, need: 198 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 199 * port-size = 32-bits = BR2[19:20] = 11 200 * no parity checking = BR2[21:22] = 00 201 * SDRAM for MSEL = BR2[24:26] = 011 202 * Valid = BR[31] = 1 203 * 204 * 0 4 8 12 16 20 24 28 205 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 206 * 207 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 208 * FIXME: the top 17 bits of BR2. 209 */ 210 211 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 212 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 213 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 214 215 /* 216 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 217 * 218 * For OR2, need: 219 * 64MB mask for AM, OR2[0:7] = 1111 1100 220 * XAM, OR2[17:18] = 11 221 * 9 columns OR2[19-21] = 010 222 * 13 rows OR2[23-25] = 100 223 * EAD set for extra time OR[31] = 1 224 * 225 * 0 4 8 12 16 20 24 28 226 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 227 */ 228 229 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 230 231 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 232 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 233 234 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ 235 | LSDMR_BSMA1516 \ 236 | LSDMR_RFCR8 \ 237 | LSDMR_PRETOACT6 \ 238 | LSDMR_ACTTORW3 \ 239 | LSDMR_BL8 \ 240 | LSDMR_WRC3 \ 241 | LSDMR_CL3 \ 242 ) 243 244 /* 245 * SDRAM Controller configuration sequence. 246 */ 247 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 248 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 249 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 250 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 251 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 252 #endif 253 254 /* 255 * Serial Port 256 */ 257 #define CONFIG_CONS_INDEX 1 258 #undef CONFIG_SERIAL_SOFTWARE_FIFO 259 #define CONFIG_SYS_NS16550 260 #define CONFIG_SYS_NS16550_SERIAL 261 #define CONFIG_SYS_NS16550_REG_SIZE 1 262 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 263 264 #define CONFIG_SYS_BAUDRATE_TABLE \ 265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 266 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 269 270 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 271 /* Use the HUSH parser */ 272 #define CONFIG_SYS_HUSH_PARSER 273 #ifdef CONFIG_SYS_HUSH_PARSER 274 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 275 #endif 276 277 /* pass open firmware flat tree */ 278 #define CONFIG_OF_LIBFDT 1 279 #define CONFIG_OF_BOARD_SETUP 1 280 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 281 282 /* I2C */ 283 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 284 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 285 #define CONFIG_FSL_I2C 286 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 287 #define CONFIG_SYS_I2C_SLAVE 0x7F 288 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 289 #define CONFIG_SYS_I2C1_OFFSET 0x3000 290 #define CONFIG_SYS_I2C2_OFFSET 0x3100 291 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET 292 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 293 294 /* TSEC */ 295 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 296 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 297 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 298 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 299 300 /* 301 * General PCI 302 * Addresses are mapped 1-1. 303 */ 304 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 305 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 306 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 307 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 308 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 309 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 310 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 311 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 312 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 313 314 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 315 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 316 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 317 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 318 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 319 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 320 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 321 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 322 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 323 324 #if defined(CONFIG_PCI) 325 326 #define PCI_64BIT 327 #define PCI_ONE_PCI1 328 #if defined(PCI_64BIT) 329 #undef PCI_ALL_PCI1 330 #undef PCI_TWO_PCI1 331 #undef PCI_ONE_PCI1 332 #endif 333 334 #define CONFIG_NET_MULTI 335 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 336 337 #undef CONFIG_EEPRO100 338 #undef CONFIG_TULIP 339 340 #if !defined(CONFIG_PCI_PNP) 341 #define PCI_ENET0_IOADDR 0xFIXME 342 #define PCI_ENET0_MEMADDR 0xFIXME 343 #define PCI_IDSEL_NUMBER 0xFIXME 344 #endif 345 346 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 347 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 348 349 #endif /* CONFIG_PCI */ 350 351 /* 352 * TSEC configuration 353 */ 354 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 355 356 #if defined(CONFIG_TSEC_ENET) 357 #ifndef CONFIG_NET_MULTI 358 #define CONFIG_NET_MULTI 1 359 #endif 360 361 #define CONFIG_TSEC1 1 362 #define CONFIG_TSEC1_NAME "TSEC0" 363 #define CONFIG_TSEC2 1 364 #define CONFIG_TSEC2_NAME "TSEC1" 365 #define CONFIG_PHY_BCM5421S 1 366 #define TSEC1_PHY_ADDR 0x19 367 #define TSEC2_PHY_ADDR 0x1a 368 #define TSEC1_PHYIDX 0 369 #define TSEC2_PHYIDX 0 370 #define TSEC1_FLAGS TSEC_GIGABIT 371 #define TSEC2_FLAGS TSEC_GIGABIT 372 373 /* Options are: TSEC[0-1] */ 374 #define CONFIG_ETHPRIME "TSEC0" 375 376 #endif /* CONFIG_TSEC_ENET */ 377 378 /* 379 * Environment 380 */ 381 #ifndef CONFIG_SYS_RAMBOOT 382 #define CONFIG_ENV_IS_IN_FLASH 1 383 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 384 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 385 #define CONFIG_ENV_SIZE 0x2000 386 387 /* Address and size of Redundant Environment Sector */ 388 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 389 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 390 391 #else 392 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 393 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 394 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 395 #define CONFIG_ENV_SIZE 0x2000 396 #endif 397 398 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 399 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 400 401 402 /* 403 * BOOTP options 404 */ 405 #define CONFIG_BOOTP_BOOTFILESIZE 406 #define CONFIG_BOOTP_BOOTPATH 407 #define CONFIG_BOOTP_GATEWAY 408 #define CONFIG_BOOTP_HOSTNAME 409 410 411 /* 412 * Command line configuration. 413 */ 414 #include <config_cmd_default.h> 415 416 #define CONFIG_CMD_I2C 417 #define CONFIG_CMD_MII 418 #define CONFIG_CMD_PING 419 420 #if defined(CONFIG_PCI) 421 #define CONFIG_CMD_PCI 422 #endif 423 424 #if defined(CONFIG_SYS_RAMBOOT) 425 #undef CONFIG_CMD_SAVEENV 426 #undef CONFIG_CMD_LOADS 427 #endif 428 429 430 #undef CONFIG_WATCHDOG /* watchdog disabled */ 431 432 /* 433 * Miscellaneous configurable options 434 */ 435 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 436 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 437 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 438 439 #if defined(CONFIG_CMD_KGDB) 440 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 441 #else 442 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 443 #endif 444 445 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 446 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 447 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 448 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 449 450 /* 451 * For booting Linux, the board info and command line data 452 * have to be in the first 8 MB of memory, since this is 453 * the maximum mapped by the Linux kernel during initialization. 454 */ 455 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 456 457 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 458 459 #if 1 /*528/264*/ 460 #define CONFIG_SYS_HRCW_LOW (\ 461 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 462 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 463 HRCWL_CSB_TO_CLKIN |\ 464 HRCWL_VCO_1X2 |\ 465 HRCWL_CORE_TO_CSB_2X1) 466 #elif 0 /*396/132*/ 467 #define CONFIG_SYS_HRCW_LOW (\ 468 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 469 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 470 HRCWL_CSB_TO_CLKIN |\ 471 HRCWL_VCO_1X4 |\ 472 HRCWL_CORE_TO_CSB_3X1) 473 #elif 0 /*264/132*/ 474 #define CONFIG_SYS_HRCW_LOW (\ 475 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 476 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 477 HRCWL_CSB_TO_CLKIN |\ 478 HRCWL_VCO_1X4 |\ 479 HRCWL_CORE_TO_CSB_2X1) 480 #elif 0 /*132/132*/ 481 #define CONFIG_SYS_HRCW_LOW (\ 482 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 483 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 484 HRCWL_CSB_TO_CLKIN |\ 485 HRCWL_VCO_1X4 |\ 486 HRCWL_CORE_TO_CSB_1X1) 487 #elif 0 /*264/264 */ 488 #define CONFIG_SYS_HRCW_LOW (\ 489 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 490 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 491 HRCWL_CSB_TO_CLKIN |\ 492 HRCWL_VCO_1X4 |\ 493 HRCWL_CORE_TO_CSB_1X1) 494 #endif 495 496 #if defined(PCI_64BIT) 497 #define CONFIG_SYS_HRCW_HIGH (\ 498 HRCWH_PCI_HOST |\ 499 HRCWH_64_BIT_PCI |\ 500 HRCWH_PCI1_ARBITER_ENABLE |\ 501 HRCWH_PCI2_ARBITER_DISABLE |\ 502 HRCWH_CORE_ENABLE |\ 503 HRCWH_FROM_0X00000100 |\ 504 HRCWH_BOOTSEQ_DISABLE |\ 505 HRCWH_SW_WATCHDOG_DISABLE |\ 506 HRCWH_ROM_LOC_LOCAL_16BIT |\ 507 HRCWH_TSEC1M_IN_GMII |\ 508 HRCWH_TSEC2M_IN_GMII ) 509 #else 510 #define CONFIG_SYS_HRCW_HIGH (\ 511 HRCWH_PCI_HOST |\ 512 HRCWH_32_BIT_PCI |\ 513 HRCWH_PCI1_ARBITER_ENABLE |\ 514 HRCWH_PCI2_ARBITER_ENABLE |\ 515 HRCWH_CORE_ENABLE |\ 516 HRCWH_FROM_0X00000100 |\ 517 HRCWH_BOOTSEQ_DISABLE |\ 518 HRCWH_SW_WATCHDOG_DISABLE |\ 519 HRCWH_ROM_LOC_LOCAL_16BIT |\ 520 HRCWH_TSEC1M_IN_GMII |\ 521 HRCWH_TSEC2M_IN_GMII ) 522 #endif 523 524 /* System IO Config */ 525 #define CONFIG_SYS_SICRH 0 526 #define CONFIG_SYS_SICRL SICRL_LDP_A 527 528 #define CONFIG_SYS_HID0_INIT 0x000000000 529 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 530 531 /* #define CONFIG_SYS_HID0_FINAL (\ 532 HID0_ENABLE_INSTRUCTION_CACHE |\ 533 HID0_ENABLE_M_BIT |\ 534 HID0_ENABLE_ADDRESS_BROADCAST ) */ 535 536 537 #define CONFIG_SYS_HID2 HID2_HBE 538 539 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 540 541 /* DDR @ 0x00000000 */ 542 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 543 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 544 545 /* PCI @ 0x80000000 */ 546 #ifdef CONFIG_PCI 547 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 548 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 549 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 550 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 551 #else 552 #define CONFIG_SYS_IBAT1L (0) 553 #define CONFIG_SYS_IBAT1U (0) 554 #define CONFIG_SYS_IBAT2L (0) 555 #define CONFIG_SYS_IBAT2U (0) 556 #endif 557 558 #ifdef CONFIG_MPC83XX_PCI2 559 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 560 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 561 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 562 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 563 #else 564 #define CONFIG_SYS_IBAT3L (0) 565 #define CONFIG_SYS_IBAT3U (0) 566 #define CONFIG_SYS_IBAT4L (0) 567 #define CONFIG_SYS_IBAT4U (0) 568 #endif 569 570 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 571 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 572 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 573 574 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 575 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 576 BATL_GUARDEDSTORAGE) 577 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 578 579 #define CONFIG_SYS_IBAT7L (0) 580 #define CONFIG_SYS_IBAT7U (0) 581 582 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 583 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 584 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 585 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 586 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 587 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 588 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 589 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 590 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 591 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 592 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 593 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 594 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 595 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 596 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 597 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 598 599 /* 600 * Internal Definitions 601 * 602 * Boot Flags 603 */ 604 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 605 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 606 607 #if defined(CONFIG_CMD_KGDB) 608 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 609 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 610 #endif 611 612 /* 613 * Environment Configuration 614 */ 615 #define CONFIG_ENV_OVERWRITE 616 617 #if defined(CONFIG_TSEC_ENET) 618 #define CONFIG_HAS_ETH0 619 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 620 #define CONFIG_HAS_ETH1 621 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 622 #endif 623 624 #define CONFIG_IPADDR 192.168.1.234 625 626 #define CONFIG_HOSTNAME SBC8349 627 #define CONFIG_ROOTPATH /tftpboot/rootfs 628 #define CONFIG_BOOTFILE uImage 629 630 #define CONFIG_SERVERIP 192.168.1.1 631 #define CONFIG_GATEWAYIP 192.168.1.1 632 #define CONFIG_NETMASK 255.255.255.0 633 634 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 635 636 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 637 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 638 639 #define CONFIG_BAUDRATE 115200 640 641 #define CONFIG_EXTRA_ENV_SETTINGS \ 642 "netdev=eth0\0" \ 643 "hostname=sbc8349\0" \ 644 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 645 "nfsroot=${serverip}:${rootpath}\0" \ 646 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 647 "addip=setenv bootargs ${bootargs} " \ 648 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 649 ":${hostname}:${netdev}:off panic=1\0" \ 650 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 651 "flash_nfs=run nfsargs addip addtty;" \ 652 "bootm ${kernel_addr}\0" \ 653 "flash_self=run ramargs addip addtty;" \ 654 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 655 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 656 "bootm\0" \ 657 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 658 "update=protect off ff800000 ff83ffff; " \ 659 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 660 "upd=run load update\0" \ 661 "fdtaddr=400000\0" \ 662 "fdtfile=sbc8349.dtb\0" \ 663 "" 664 665 #define CONFIG_NFSBOOTCOMMAND \ 666 "setenv bootargs root=/dev/nfs rw " \ 667 "nfsroot=$serverip:$rootpath " \ 668 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 669 "console=$consoledev,$baudrate $othbootargs;" \ 670 "tftp $loadaddr $bootfile;" \ 671 "tftp $fdtaddr $fdtfile;" \ 672 "bootm $loadaddr - $fdtaddr" 673 674 #define CONFIG_RAMBOOTCOMMAND \ 675 "setenv bootargs root=/dev/ram rw " \ 676 "console=$consoledev,$baudrate $othbootargs;" \ 677 "tftp $ramdiskaddr $ramdiskfile;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr $ramdiskaddr $fdtaddr" 681 682 #define CONFIG_BOOTCOMMAND "run flash_self" 683 684 #endif /* __CONFIG_H */ 685