1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 39 #define CONFIG_MPC834x 1 /* MPC834x family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 42 43 #define CONFIG_SYS_TEXT_BASE 0xFF800000 44 45 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 46 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 47 48 /* 49 * The default if PCI isn't enabled, or if no PCI clk setting is given 50 * is 66MHz; this is what the board defaults to when the PCI slot is 51 * physically empty. The board will automatically (i.e w/o jumpers) 52 * clock down to 33MHz if you insert a 33MHz PCI card. 53 */ 54 #ifdef CONFIG_PCI_33M 55 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 56 #else /* 66M */ 57 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 58 #endif 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #ifdef CONFIG_PCI_33M 62 #define CONFIG_SYS_CLK_FREQ 33000000 63 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 64 #else /* 66M */ 65 #define CONFIG_SYS_CLK_FREQ 66000000 66 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 67 #endif 68 #endif 69 70 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 71 72 #define CONFIG_SYS_IMMR 0xE0000000 73 74 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 75 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 76 #define CONFIG_SYS_MEMTEST_END 0x00100000 77 78 /* 79 * DDR Setup 80 */ 81 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 82 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 83 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 84 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 85 86 /* 87 * 32-bit data path mode. 88 * 89 * Please note that using this mode for devices with the real density of 64-bit 90 * effectively reduces the amount of available memory due to the effect of 91 * wrapping around while translating address to row/columns, for example in the 92 * 256MB module the upper 128MB get aliased with contents of the lower 93 * 128MB); normally this define should be used for devices with real 32-bit 94 * data path. 95 */ 96 #undef CONFIG_DDR_32BIT 97 98 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 100 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 102 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 103 #define CONFIG_DDR_2T_TIMING 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 110 111 #else 112 /* 113 * Manually set up DDR parameters 114 * NB: manual DDR setup untested on sbc834x 115 */ 116 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 117 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 118 | CSCONFIG_ROW_BIT_13 \ 119 | CSCONFIG_COL_BIT_10) 120 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 124 125 #if defined(CONFIG_DDR_32BIT) 126 /* set burst length to 8 for 32-bit data path */ 127 /* DLL,normal,seq,4/2.5, 8 burst len */ 128 #define CONFIG_SYS_DDR_MODE 0x00000023 129 #else 130 /* the default burst length is 4 - for 64-bit data path */ 131 /* DLL,normal,seq,4/2.5, 4 burst len */ 132 #define CONFIG_SYS_DDR_MODE 0x00000022 133 #endif 134 #endif 135 136 /* 137 * SDRAM on the Local Bus 138 */ 139 #define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 140 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 141 142 /* 143 * FLASH on the Local Bus 144 */ 145 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 146 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 147 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 148 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 149 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 150 151 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 152 | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 153 | BR_V) /* valid */ 154 155 #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 156 /* window base at flash base */ 157 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 158 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 159 160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 162 163 #undef CONFIG_SYS_FLASH_CHECKSUM 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 168 169 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 170 #define CONFIG_SYS_RAMBOOT 171 #else 172 #undef CONFIG_SYS_RAMBOOT 173 #endif 174 175 #define CONFIG_SYS_INIT_RAM_LOCK 1 176 /* Initial RAM address */ 177 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 178 /* Size of used area in RAM*/ 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 180 181 #define CONFIG_SYS_GBL_DATA_OFFSET \ 182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 185 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 186 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 187 188 /* 189 * Local Bus LCRR and LBCR regs 190 * LCRR: DLL bypass, Clock divider is 4 191 * External Local Bus rate is 192 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 193 */ 194 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 195 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 196 #define CONFIG_SYS_LBC_LBCR 0x00000000 197 198 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 199 200 #ifdef CONFIG_SYS_LB_SDRAM 201 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 202 /* 203 * Base Register 2 and Option Register 2 configure SDRAM. 204 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 205 * 206 * For BR2, need: 207 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 208 * port-size = 32-bits = BR2[19:20] = 11 209 * no parity checking = BR2[21:22] = 00 210 * SDRAM for MSEL = BR2[24:26] = 011 211 * Valid = BR[31] = 1 212 * 213 * 0 4 8 12 16 20 24 28 214 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 215 * 216 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 217 * FIXME: the top 17 bits of BR2. 218 */ 219 220 /* Port-size=32bit, MSEL=SDRAM */ 221 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 222 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 223 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 224 225 /* 226 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 227 * 228 * For OR2, need: 229 * 64MB mask for AM, OR2[0:7] = 1111 1100 230 * XAM, OR2[17:18] = 11 231 * 9 columns OR2[19-21] = 010 232 * 13 rows OR2[23-25] = 100 233 * EAD set for extra time OR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 237 */ 238 239 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 240 241 /* LB sdram refresh timer, about 6us */ 242 #define CONFIG_SYS_LBC_LSRT 0x32000000 243 /* LB refresh timer prescal, 266MHz/32 */ 244 #define CONFIG_SYS_LBC_MRTPR 0x20000000 245 246 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 247 | LSDMR_BSMA1516 \ 248 | LSDMR_RFCR8 \ 249 | LSDMR_PRETOACT6 \ 250 | LSDMR_ACTTORW3 \ 251 | LSDMR_BL8 \ 252 | LSDMR_WRC3 \ 253 | LSDMR_CL3) 254 255 /* 256 * SDRAM Controller configuration sequence. 257 */ 258 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 259 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 260 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 261 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 262 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 263 #endif 264 265 /* 266 * Serial Port 267 */ 268 #define CONFIG_CONS_INDEX 1 269 #define CONFIG_SYS_NS16550 270 #define CONFIG_SYS_NS16550_SERIAL 271 #define CONFIG_SYS_NS16550_REG_SIZE 1 272 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 273 274 #define CONFIG_SYS_BAUDRATE_TABLE \ 275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 276 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 279 280 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 281 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 282 /* Use the HUSH parser */ 283 #define CONFIG_SYS_HUSH_PARSER 284 #ifdef CONFIG_SYS_HUSH_PARSER 285 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 286 #endif 287 288 /* pass open firmware flat tree */ 289 #define CONFIG_OF_LIBFDT 1 290 #define CONFIG_OF_BOARD_SETUP 1 291 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 292 293 /* I2C */ 294 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 295 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 296 #define CONFIG_FSL_I2C 297 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 298 #define CONFIG_SYS_I2C_SLAVE 0x7F 299 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 300 #define CONFIG_SYS_I2C1_OFFSET 0x3000 301 #define CONFIG_SYS_I2C2_OFFSET 0x3100 302 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET 303 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 304 305 /* TSEC */ 306 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 307 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 308 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 309 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 316 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 317 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 319 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 320 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 322 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 323 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 324 325 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 326 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 327 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 328 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 329 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 330 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 331 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 332 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 333 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 334 335 #if defined(CONFIG_PCI) 336 337 #define PCI_64BIT 338 #define PCI_ONE_PCI1 339 #if defined(PCI_64BIT) 340 #undef PCI_ALL_PCI1 341 #undef PCI_TWO_PCI1 342 #undef PCI_ONE_PCI1 343 #endif 344 345 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 346 347 #undef CONFIG_EEPRO100 348 #undef CONFIG_TULIP 349 350 #if !defined(CONFIG_PCI_PNP) 351 #define PCI_ENET0_IOADDR 0xFIXME 352 #define PCI_ENET0_MEMADDR 0xFIXME 353 #define PCI_IDSEL_NUMBER 0xFIXME 354 #endif 355 356 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 357 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 358 359 #endif /* CONFIG_PCI */ 360 361 /* 362 * TSEC configuration 363 */ 364 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 365 366 #if defined(CONFIG_TSEC_ENET) 367 368 #define CONFIG_TSEC1 1 369 #define CONFIG_TSEC1_NAME "TSEC0" 370 #define CONFIG_TSEC2 1 371 #define CONFIG_TSEC2_NAME "TSEC1" 372 #define CONFIG_PHY_BCM5421S 1 373 #define TSEC1_PHY_ADDR 0x19 374 #define TSEC2_PHY_ADDR 0x1a 375 #define TSEC1_PHYIDX 0 376 #define TSEC2_PHYIDX 0 377 #define TSEC1_FLAGS TSEC_GIGABIT 378 #define TSEC2_FLAGS TSEC_GIGABIT 379 380 /* Options are: TSEC[0-1] */ 381 #define CONFIG_ETHPRIME "TSEC0" 382 383 #endif /* CONFIG_TSEC_ENET */ 384 385 /* 386 * Environment 387 */ 388 #ifndef CONFIG_SYS_RAMBOOT 389 #define CONFIG_ENV_IS_IN_FLASH 1 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 391 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 392 #define CONFIG_ENV_SIZE 0x2000 393 394 /* Address and size of Redundant Environment Sector */ 395 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 396 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 397 398 #else 399 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 400 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 401 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 402 #define CONFIG_ENV_SIZE 0x2000 403 #endif 404 405 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 406 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 407 408 409 /* 410 * BOOTP options 411 */ 412 #define CONFIG_BOOTP_BOOTFILESIZE 413 #define CONFIG_BOOTP_BOOTPATH 414 #define CONFIG_BOOTP_GATEWAY 415 #define CONFIG_BOOTP_HOSTNAME 416 417 418 /* 419 * Command line configuration. 420 */ 421 #include <config_cmd_default.h> 422 423 #define CONFIG_CMD_I2C 424 #define CONFIG_CMD_MII 425 #define CONFIG_CMD_PING 426 427 #if defined(CONFIG_PCI) 428 #define CONFIG_CMD_PCI 429 #endif 430 431 #if defined(CONFIG_SYS_RAMBOOT) 432 #undef CONFIG_CMD_SAVEENV 433 #undef CONFIG_CMD_LOADS 434 #endif 435 436 437 #undef CONFIG_WATCHDOG /* watchdog disabled */ 438 439 /* 440 * Miscellaneous configurable options 441 */ 442 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 443 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 444 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 445 446 #if defined(CONFIG_CMD_KGDB) 447 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 448 #else 449 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 450 #endif 451 452 /* Print Buffer Size */ 453 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 454 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 455 /* Boot Argument Buffer Size */ 456 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 457 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 458 459 /* 460 * For booting Linux, the board info and command line data 461 * have to be in the first 256 MB of memory, since this is 462 * the maximum mapped by the Linux kernel during initialization. 463 */ 464 /* Initial Memory map for Linux*/ 465 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 466 467 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 468 469 #if 1 /*528/264*/ 470 #define CONFIG_SYS_HRCW_LOW (\ 471 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 472 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 473 HRCWL_CSB_TO_CLKIN |\ 474 HRCWL_VCO_1X2 |\ 475 HRCWL_CORE_TO_CSB_2X1) 476 #elif 0 /*396/132*/ 477 #define CONFIG_SYS_HRCW_LOW (\ 478 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 479 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 480 HRCWL_CSB_TO_CLKIN |\ 481 HRCWL_VCO_1X4 |\ 482 HRCWL_CORE_TO_CSB_3X1) 483 #elif 0 /*264/132*/ 484 #define CONFIG_SYS_HRCW_LOW (\ 485 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 486 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 487 HRCWL_CSB_TO_CLKIN |\ 488 HRCWL_VCO_1X4 |\ 489 HRCWL_CORE_TO_CSB_2X1) 490 #elif 0 /*132/132*/ 491 #define CONFIG_SYS_HRCW_LOW (\ 492 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 493 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 494 HRCWL_CSB_TO_CLKIN |\ 495 HRCWL_VCO_1X4 |\ 496 HRCWL_CORE_TO_CSB_1X1) 497 #elif 0 /*264/264 */ 498 #define CONFIG_SYS_HRCW_LOW (\ 499 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 500 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 501 HRCWL_CSB_TO_CLKIN |\ 502 HRCWL_VCO_1X4 |\ 503 HRCWL_CORE_TO_CSB_1X1) 504 #endif 505 506 #if defined(PCI_64BIT) 507 #define CONFIG_SYS_HRCW_HIGH (\ 508 HRCWH_PCI_HOST |\ 509 HRCWH_64_BIT_PCI |\ 510 HRCWH_PCI1_ARBITER_ENABLE |\ 511 HRCWH_PCI2_ARBITER_DISABLE |\ 512 HRCWH_CORE_ENABLE |\ 513 HRCWH_FROM_0X00000100 |\ 514 HRCWH_BOOTSEQ_DISABLE |\ 515 HRCWH_SW_WATCHDOG_DISABLE |\ 516 HRCWH_ROM_LOC_LOCAL_16BIT |\ 517 HRCWH_TSEC1M_IN_GMII |\ 518 HRCWH_TSEC2M_IN_GMII) 519 #else 520 #define CONFIG_SYS_HRCW_HIGH (\ 521 HRCWH_PCI_HOST |\ 522 HRCWH_32_BIT_PCI |\ 523 HRCWH_PCI1_ARBITER_ENABLE |\ 524 HRCWH_PCI2_ARBITER_ENABLE |\ 525 HRCWH_CORE_ENABLE |\ 526 HRCWH_FROM_0X00000100 |\ 527 HRCWH_BOOTSEQ_DISABLE |\ 528 HRCWH_SW_WATCHDOG_DISABLE |\ 529 HRCWH_ROM_LOC_LOCAL_16BIT |\ 530 HRCWH_TSEC1M_IN_GMII |\ 531 HRCWH_TSEC2M_IN_GMII) 532 #endif 533 534 /* System IO Config */ 535 #define CONFIG_SYS_SICRH 0 536 #define CONFIG_SYS_SICRL SICRL_LDP_A 537 538 #define CONFIG_SYS_HID0_INIT 0x000000000 539 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 540 | HID0_ENABLE_INSTRUCTION_CACHE) 541 542 /* #define CONFIG_SYS_HID0_FINAL (\ 543 HID0_ENABLE_INSTRUCTION_CACHE |\ 544 HID0_ENABLE_M_BIT |\ 545 HID0_ENABLE_ADDRESS_BROADCAST) */ 546 547 548 #define CONFIG_SYS_HID2 HID2_HBE 549 550 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 551 552 /* DDR @ 0x00000000 */ 553 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 554 | BATL_PP_10 \ 555 | BATL_MEMCOHERENCE) 556 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 557 | BATU_BL_256M \ 558 | BATU_VS \ 559 | BATU_VP) 560 561 /* PCI @ 0x80000000 */ 562 #ifdef CONFIG_PCI 563 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 564 | BATL_PP_10 \ 565 | BATL_MEMCOHERENCE) 566 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 567 | BATU_BL_256M \ 568 | BATU_VS \ 569 | BATU_VP) 570 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 571 | BATL_PP_10 \ 572 | BATL_CACHEINHIBIT \ 573 | BATL_GUARDEDSTORAGE) 574 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 575 | BATU_BL_256M \ 576 | BATU_VS \ 577 | BATU_VP) 578 #else 579 #define CONFIG_SYS_IBAT1L (0) 580 #define CONFIG_SYS_IBAT1U (0) 581 #define CONFIG_SYS_IBAT2L (0) 582 #define CONFIG_SYS_IBAT2U (0) 583 #endif 584 585 #ifdef CONFIG_MPC83XX_PCI2 586 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 587 | BATL_PP_10 \ 588 | BATL_MEMCOHERENCE) 589 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 590 | BATU_BL_256M \ 591 | BATU_VS \ 592 | BATU_VP) 593 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 594 | BATL_PP_10 \ 595 | BATL_CACHEINHIBIT \ 596 | BATL_GUARDEDSTORAGE) 597 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 598 | BATU_BL_256M \ 599 | BATU_VS \ 600 | BATU_VP) 601 #else 602 #define CONFIG_SYS_IBAT3L (0) 603 #define CONFIG_SYS_IBAT3U (0) 604 #define CONFIG_SYS_IBAT4L (0) 605 #define CONFIG_SYS_IBAT4U (0) 606 #endif 607 608 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 609 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 610 | BATL_PP_10 \ 611 | BATL_CACHEINHIBIT \ 612 | BATL_GUARDEDSTORAGE) 613 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 614 | BATU_BL_256M \ 615 | BATU_VS \ 616 | BATU_VP) 617 618 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 619 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 620 | BATL_PP_10 \ 621 | BATL_MEMCOHERENCE \ 622 | BATL_GUARDEDSTORAGE) 623 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 624 625 #define CONFIG_SYS_IBAT7L (0) 626 #define CONFIG_SYS_IBAT7U (0) 627 628 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 629 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 630 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 631 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 632 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 633 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 634 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 635 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 636 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 637 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 638 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 639 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 640 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 641 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 642 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 643 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 644 645 #if defined(CONFIG_CMD_KGDB) 646 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 647 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 648 #endif 649 650 /* 651 * Environment Configuration 652 */ 653 #define CONFIG_ENV_OVERWRITE 654 655 #if defined(CONFIG_TSEC_ENET) 656 #define CONFIG_HAS_ETH0 657 #define CONFIG_HAS_ETH1 658 #endif 659 660 #define CONFIG_HOSTNAME SBC8349 661 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 662 #define CONFIG_BOOTFILE "uImage" 663 664 /* default location for tftp and bootm */ 665 #define CONFIG_LOADADDR 800000 666 667 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 668 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 669 670 #define CONFIG_BAUDRATE 115200 671 672 #define CONFIG_EXTRA_ENV_SETTINGS \ 673 "netdev=eth0\0" \ 674 "hostname=sbc8349\0" \ 675 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 676 "nfsroot=${serverip}:${rootpath}\0" \ 677 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 678 "addip=setenv bootargs ${bootargs} " \ 679 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 680 ":${hostname}:${netdev}:off panic=1\0" \ 681 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 682 "flash_nfs=run nfsargs addip addtty;" \ 683 "bootm ${kernel_addr}\0" \ 684 "flash_self=run ramargs addip addtty;" \ 685 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 686 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 687 "bootm\0" \ 688 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 689 "update=protect off ff800000 ff83ffff; " \ 690 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 691 "upd=run load update\0" \ 692 "fdtaddr=780000\0" \ 693 "fdtfile=sbc8349.dtb\0" \ 694 "" 695 696 #define CONFIG_NFSBOOTCOMMAND \ 697 "setenv bootargs root=/dev/nfs rw " \ 698 "nfsroot=$serverip:$rootpath " \ 699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 700 "$netdev:off " \ 701 "console=$consoledev,$baudrate $othbootargs;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr - $fdtaddr" 705 706 #define CONFIG_RAMBOOTCOMMAND \ 707 "setenv bootargs root=/dev/ram rw " \ 708 "console=$consoledev,$baudrate $othbootargs;" \ 709 "tftp $ramdiskaddr $ramdiskfile;" \ 710 "tftp $loadaddr $bootfile;" \ 711 "tftp $fdtaddr $fdtfile;" \ 712 "bootm $loadaddr $ramdiskaddr $fdtaddr" 713 714 #define CONFIG_BOOTCOMMAND "run flash_self" 715 716 #endif /* __CONFIG_H */ 717