1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 #undef DEBUG 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_E300 1 /* E300 Family */ 40 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 41 #define CONFIG_MPC834X 1 /* MPC834X family */ 42 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 43 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 44 45 #undef CONFIG_PCI 46 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 47 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 48 49 #define PCI_66M 50 #ifdef PCI_66M 51 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 52 #else 53 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 54 #endif 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #ifdef PCI_66M 58 #define CONFIG_SYS_CLK_FREQ 66000000 59 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 60 #else 61 #define CONFIG_SYS_CLK_FREQ 33000000 62 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 63 #endif 64 #endif 65 66 #define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) 67 #define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ 68 #define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ 69 #define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ 70 #define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ 71 #define CFG_SCCR_VAL ( CFG_SCCR_INIT \ 72 | CFG_SCCR_TSEC1CM \ 73 | CFG_SCCR_TSEC2CM \ 74 | CFG_SCCR_ENCCM \ 75 | CFG_SCCR_USBCM ) 76 77 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 78 79 #define CFG_IMMR 0xE0000000 80 81 #undef CFG_DRAM_TEST /* memory test, takes time */ 82 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 83 #define CFG_MEMTEST_END 0x00100000 84 85 /* 86 * DDR Setup 87 */ 88 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 89 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 90 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 91 #define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 92 93 /* 94 * 32-bit data path mode. 95 * 96 * Please note that using this mode for devices with the real density of 64-bit 97 * effectively reduces the amount of available memory due to the effect of 98 * wrapping around while translating address to row/columns, for example in the 99 * 256MB module the upper 128MB get aliased with contents of the lower 100 * 128MB); normally this define should be used for devices with real 32-bit 101 * data path. 102 */ 103 #undef CONFIG_DDR_32BIT 104 105 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 106 #define CFG_SDRAM_BASE CFG_DDR_BASE 107 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 108 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 109 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 110 #define CONFIG_DDR_2T_TIMING 111 112 #if defined(CONFIG_SPD_EEPROM) 113 /* 114 * Determine DDR configuration from I2C interface. 115 */ 116 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 117 118 #else 119 /* 120 * Manually set up DDR parameters 121 * NB: manual DDR setup untested on sbc834x 122 */ 123 #define CFG_DDR_SIZE 256 /* MB */ 124 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 125 #define CFG_DDR_TIMING_1 0x36332321 126 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 127 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 128 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 129 130 #if defined(CONFIG_DDR_32BIT) 131 /* set burst length to 8 for 32-bit data path */ 132 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 133 #else 134 /* the default burst length is 4 - for 64-bit data path */ 135 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 136 #endif 137 #endif 138 139 /* 140 * SDRAM on the Local Bus 141 */ 142 #define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 143 #define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 144 145 /* 146 * FLASH on the Local Bus 147 */ 148 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 149 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 150 #define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ 151 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 152 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 153 154 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 155 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 156 BR_V) /* valid */ 157 158 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 159 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 160 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 161 162 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 164 165 #undef CFG_FLASH_CHECKSUM 166 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CFG_MID_FLASH_JUMP 0x7F000000 170 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 171 172 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 173 #define CFG_RAMBOOT 174 #else 175 #undef CFG_RAMBOOT 176 #endif 177 178 #define CONFIG_L1_INIT_RAM 179 #define CFG_INIT_RAM_LOCK 1 180 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 181 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 182 183 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 184 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 185 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 186 187 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 188 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 189 190 /* 191 * Local Bus LCRR and LBCR regs 192 * LCRR: DLL bypass, Clock divider is 4 193 * External Local Bus rate is 194 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 195 */ 196 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 197 #define CFG_LBC_LBCR 0x00000000 198 199 #undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ 200 201 #ifdef CFG_LB_SDRAM 202 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 203 /* 204 * Base Register 2 and Option Register 2 configure SDRAM. 205 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 206 * 207 * For BR2, need: 208 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 209 * port-size = 32-bits = BR2[19:20] = 11 210 * no parity checking = BR2[21:22] = 00 211 * SDRAM for MSEL = BR2[24:26] = 011 212 * Valid = BR[31] = 1 213 * 214 * 0 4 8 12 16 20 24 28 215 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 216 * 217 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 218 * FIXME: the top 17 bits of BR2. 219 */ 220 221 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 222 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 223 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 224 225 /* 226 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 227 * 228 * For OR2, need: 229 * 64MB mask for AM, OR2[0:7] = 1111 1100 230 * XAM, OR2[17:18] = 11 231 * 9 columns OR2[19-21] = 010 232 * 13 rows OR2[23-25] = 100 233 * EAD set for extra time OR[31] = 1 234 * 235 * 0 4 8 12 16 20 24 28 236 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 237 */ 238 239 #define CFG_OR2_PRELIM 0xFC006901 240 241 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 242 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 243 244 /* 245 * LSDMR masks 246 */ 247 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 248 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 249 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 250 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 251 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 252 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 253 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 254 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 255 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 256 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 257 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 258 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 259 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 260 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 261 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 262 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 263 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 264 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 265 266 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 267 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 268 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 269 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 270 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 271 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 272 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 273 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 274 275 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 276 | CFG_LBC_LSDMR_BSMA1516 \ 277 | CFG_LBC_LSDMR_RFCR8 \ 278 | CFG_LBC_LSDMR_PRETOACT6 \ 279 | CFG_LBC_LSDMR_ACTTORW3 \ 280 | CFG_LBC_LSDMR_BL8 \ 281 | CFG_LBC_LSDMR_WRC3 \ 282 | CFG_LBC_LSDMR_CL3 \ 283 ) 284 285 /* 286 * SDRAM Controller configuration sequence. 287 */ 288 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 289 | CFG_LBC_LSDMR_OP_PCHALL) 290 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 291 | CFG_LBC_LSDMR_OP_ARFRSH) 292 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 293 | CFG_LBC_LSDMR_OP_ARFRSH) 294 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 295 | CFG_LBC_LSDMR_OP_MRW) 296 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 297 | CFG_LBC_LSDMR_OP_NORMAL) 298 #endif 299 300 /* 301 * Serial Port 302 */ 303 #define CONFIG_CONS_INDEX 1 304 #undef CONFIG_SERIAL_SOFTWARE_FIFO 305 #define CFG_NS16550 306 #define CFG_NS16550_SERIAL 307 #define CFG_NS16550_REG_SIZE 1 308 #define CFG_NS16550_CLK get_bus_freq(0) 309 310 #define CFG_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 312 313 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 314 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 315 316 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 317 /* Use the HUSH parser */ 318 #define CFG_HUSH_PARSER 319 #ifdef CFG_HUSH_PARSER 320 #define CFG_PROMPT_HUSH_PS2 "> " 321 #endif 322 323 /* pass open firmware flat tree */ 324 #define CONFIG_OF_FLAT_TREE 1 325 #define CONFIG_OF_BOARD_SETUP 1 326 327 /* maximum size of the flat tree (8K) */ 328 #define OF_FLAT_TREE_MAX_SIZE 8192 329 330 #define OF_CPU "PowerPC,8349@0" 331 #define OF_SOC "soc8349@e0000000" 332 #define OF_TBCLK (bd->bi_busfreq / 4) 333 #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" 334 335 /* I2C */ 336 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 337 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 338 #define CONFIG_FSL_I2C 339 #define CONFIG_I2C_CMD_TREE 340 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 341 #define CFG_I2C_SLAVE 0x7F 342 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 343 #define CFG_I2C1_OFFSET 0x3000 344 #define CFG_I2C2_OFFSET 0x3100 345 #define CFG_I2C_OFFSET CFG_I2C2_OFFSET 346 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 347 348 /* TSEC */ 349 #define CFG_TSEC1_OFFSET 0x24000 350 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 351 #define CFG_TSEC2_OFFSET 0x25000 352 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 353 354 /* 355 * General PCI 356 * Addresses are mapped 1-1. 357 */ 358 #define CFG_PCI1_MEM_BASE 0x80000000 359 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 360 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 361 #define CFG_PCI1_MMIO_BASE 0x90000000 362 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 363 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 364 #define CFG_PCI1_IO_BASE 0x00000000 365 #define CFG_PCI1_IO_PHYS 0xE2000000 366 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 367 368 #define CFG_PCI2_MEM_BASE 0xA0000000 369 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 370 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 371 #define CFG_PCI2_MMIO_BASE 0xB0000000 372 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 373 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 374 #define CFG_PCI2_IO_BASE 0x00000000 375 #define CFG_PCI2_IO_PHYS 0xE2100000 376 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 377 378 #if defined(CONFIG_PCI) 379 380 #define PCI_64BIT 381 #define PCI_ONE_PCI1 382 #if defined(PCI_64BIT) 383 #undef PCI_ALL_PCI1 384 #undef PCI_TWO_PCI1 385 #undef PCI_ONE_PCI1 386 #endif 387 388 #define CONFIG_NET_MULTI 389 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 390 391 #undef CONFIG_EEPRO100 392 #undef CONFIG_TULIP 393 394 #if !defined(CONFIG_PCI_PNP) 395 #define PCI_ENET0_IOADDR 0xFIXME 396 #define PCI_ENET0_MEMADDR 0xFIXME 397 #define PCI_IDSEL_NUMBER 0xFIXME 398 #endif 399 400 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 401 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 402 403 #endif /* CONFIG_PCI */ 404 405 /* 406 * TSEC configuration 407 */ 408 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 409 410 #if defined(CONFIG_TSEC_ENET) 411 #ifndef CONFIG_NET_MULTI 412 #define CONFIG_NET_MULTI 1 413 #endif 414 415 #define CONFIG_MPC83XX_TSEC1 1 416 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 417 #define CONFIG_MPC83XX_TSEC2 1 418 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 419 #define CONFIG_PHY_BCM5421S 1 420 #define TSEC1_PHY_ADDR 0x19 421 #define TSEC2_PHY_ADDR 0x1a 422 #define TSEC1_PHYIDX 0 423 #define TSEC2_PHYIDX 0 424 425 /* Options are: TSEC[0-1] */ 426 #define CONFIG_ETHPRIME "TSEC0" 427 428 #endif /* CONFIG_TSEC_ENET */ 429 430 /* 431 * Environment 432 */ 433 #ifndef CFG_RAMBOOT 434 #define CFG_ENV_IS_IN_FLASH 1 435 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 436 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 437 #define CFG_ENV_SIZE 0x2000 438 439 /* Address and size of Redundant Environment Sector */ 440 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 441 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 442 443 #else 444 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 445 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 446 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 447 #define CFG_ENV_SIZE 0x2000 448 #endif 449 450 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 451 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 452 453 #if defined(CFG_RAMBOOT) 454 #if defined(CONFIG_PCI) 455 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 456 | CFG_CMD_PING \ 457 | CFG_CMD_PCI \ 458 | CFG_CMD_I2C) \ 459 & \ 460 ~(CFG_CMD_ENV \ 461 | CFG_CMD_LOADS)) 462 #else 463 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 464 | CFG_CMD_PING \ 465 | CFG_CMD_I2C) \ 466 & \ 467 ~(CFG_CMD_ENV \ 468 | CFG_CMD_LOADS)) 469 #endif 470 #else 471 #if defined(CONFIG_PCI) 472 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 473 | CFG_CMD_PCI \ 474 | CFG_CMD_PING \ 475 | CFG_CMD_I2C \ 476 ) 477 #else 478 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 479 | CFG_CMD_PING \ 480 | CFG_CMD_I2C \ 481 | CFG_CMD_MII \ 482 ) 483 #endif 484 #endif 485 486 #include <cmd_confdefs.h> 487 488 #undef CONFIG_WATCHDOG /* watchdog disabled */ 489 490 /* 491 * Miscellaneous configurable options 492 */ 493 #define CFG_LONGHELP /* undef to save memory */ 494 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 495 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 496 497 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 498 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 499 #else 500 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 501 #endif 502 503 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 504 #define CFG_MAXARGS 16 /* max number of command args */ 505 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 506 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 507 508 /* 509 * For booting Linux, the board info and command line data 510 * have to be in the first 8 MB of memory, since this is 511 * the maximum mapped by the Linux kernel during initialization. 512 */ 513 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 514 515 /* Cache Configuration */ 516 #define CFG_DCACHE_SIZE 32768 517 #define CFG_CACHELINE_SIZE 32 518 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 519 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 520 #endif 521 522 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 523 524 #if 1 /*528/264*/ 525 #define CFG_HRCW_LOW (\ 526 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 527 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 528 HRCWL_CSB_TO_CLKIN |\ 529 HRCWL_VCO_1X2 |\ 530 HRCWL_CORE_TO_CSB_2X1) 531 #elif 0 /*396/132*/ 532 #define CFG_HRCW_LOW (\ 533 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 534 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 535 HRCWL_CSB_TO_CLKIN |\ 536 HRCWL_VCO_1X4 |\ 537 HRCWL_CORE_TO_CSB_3X1) 538 #elif 0 /*264/132*/ 539 #define CFG_HRCW_LOW (\ 540 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 541 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 542 HRCWL_CSB_TO_CLKIN |\ 543 HRCWL_VCO_1X4 |\ 544 HRCWL_CORE_TO_CSB_2X1) 545 #elif 0 /*132/132*/ 546 #define CFG_HRCW_LOW (\ 547 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 548 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 549 HRCWL_CSB_TO_CLKIN |\ 550 HRCWL_VCO_1X4 |\ 551 HRCWL_CORE_TO_CSB_1X1) 552 #elif 0 /*264/264 */ 553 #define CFG_HRCW_LOW (\ 554 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 555 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 556 HRCWL_CSB_TO_CLKIN |\ 557 HRCWL_VCO_1X4 |\ 558 HRCWL_CORE_TO_CSB_1X1) 559 #endif 560 561 #if defined(PCI_64BIT) 562 #define CFG_HRCW_HIGH (\ 563 HRCWH_PCI_HOST |\ 564 HRCWH_64_BIT_PCI |\ 565 HRCWH_PCI1_ARBITER_ENABLE |\ 566 HRCWH_PCI2_ARBITER_DISABLE |\ 567 HRCWH_CORE_ENABLE |\ 568 HRCWH_FROM_0X00000100 |\ 569 HRCWH_BOOTSEQ_DISABLE |\ 570 HRCWH_SW_WATCHDOG_DISABLE |\ 571 HRCWH_ROM_LOC_LOCAL_16BIT |\ 572 HRCWH_TSEC1M_IN_GMII |\ 573 HRCWH_TSEC2M_IN_GMII ) 574 #else 575 #define CFG_HRCW_HIGH (\ 576 HRCWH_PCI_HOST |\ 577 HRCWH_32_BIT_PCI |\ 578 HRCWH_PCI1_ARBITER_ENABLE |\ 579 HRCWH_PCI2_ARBITER_ENABLE |\ 580 HRCWH_CORE_ENABLE |\ 581 HRCWH_FROM_0X00000100 |\ 582 HRCWH_BOOTSEQ_DISABLE |\ 583 HRCWH_SW_WATCHDOG_DISABLE |\ 584 HRCWH_ROM_LOC_LOCAL_16BIT |\ 585 HRCWH_TSEC1M_IN_GMII |\ 586 HRCWH_TSEC2M_IN_GMII ) 587 #endif 588 589 /* System IO Config */ 590 #define CFG_SICRH SICRH_TSOBI1 591 #define CFG_SICRL SICRL_LDP_A 592 593 #define CFG_HID0_INIT 0x000000000 594 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 595 596 /* #define CFG_HID0_FINAL (\ 597 HID0_ENABLE_INSTRUCTION_CACHE |\ 598 HID0_ENABLE_M_BIT |\ 599 HID0_ENABLE_ADDRESS_BROADCAST ) */ 600 601 602 #define CFG_HID2 HID2_HBE 603 604 /* DDR @ 0x00000000 */ 605 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 606 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 607 608 /* PCI @ 0x80000000 */ 609 #ifdef CONFIG_PCI 610 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 611 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 612 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 613 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 614 #else 615 #define CFG_IBAT1L (0) 616 #define CFG_IBAT1U (0) 617 #define CFG_IBAT2L (0) 618 #define CFG_IBAT2U (0) 619 #endif 620 621 #ifdef CONFIG_MPC83XX_PCI2 622 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 623 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 624 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 625 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 626 #else 627 #define CFG_IBAT3L (0) 628 #define CFG_IBAT3U (0) 629 #define CFG_IBAT4L (0) 630 #define CFG_IBAT4U (0) 631 #endif 632 633 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 634 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 635 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 636 637 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 638 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 639 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 640 641 #define CFG_IBAT7L (0) 642 #define CFG_IBAT7U (0) 643 644 #define CFG_DBAT0L CFG_IBAT0L 645 #define CFG_DBAT0U CFG_IBAT0U 646 #define CFG_DBAT1L CFG_IBAT1L 647 #define CFG_DBAT1U CFG_IBAT1U 648 #define CFG_DBAT2L CFG_IBAT2L 649 #define CFG_DBAT2U CFG_IBAT2U 650 #define CFG_DBAT3L CFG_IBAT3L 651 #define CFG_DBAT3U CFG_IBAT3U 652 #define CFG_DBAT4L CFG_IBAT4L 653 #define CFG_DBAT4U CFG_IBAT4U 654 #define CFG_DBAT5L CFG_IBAT5L 655 #define CFG_DBAT5U CFG_IBAT5U 656 #define CFG_DBAT6L CFG_IBAT6L 657 #define CFG_DBAT6U CFG_IBAT6U 658 #define CFG_DBAT7L CFG_IBAT7L 659 #define CFG_DBAT7U CFG_IBAT7U 660 661 /* 662 * Internal Definitions 663 * 664 * Boot Flags 665 */ 666 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 667 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 668 669 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 671 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 672 #endif 673 674 /* 675 * Environment Configuration 676 */ 677 #define CONFIG_ENV_OVERWRITE 678 679 #if defined(CONFIG_TSEC_ENET) 680 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 681 #define CONFIG_HAS_ETH1 682 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 683 #endif 684 685 #define CONFIG_IPADDR 192.168.1.234 686 687 #define CONFIG_HOSTNAME SBC8349 688 #define CONFIG_ROOTPATH /tftpboot/rootfs 689 #define CONFIG_BOOTFILE uImage 690 691 #define CONFIG_SERVERIP 192.168.1.1 692 #define CONFIG_GATEWAYIP 192.168.1.1 693 #define CONFIG_NETMASK 255.255.255.0 694 695 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 696 697 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 698 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 699 700 #define CONFIG_BAUDRATE 115200 701 702 #define CONFIG_EXTRA_ENV_SETTINGS \ 703 "netdev=eth0\0" \ 704 "hostname=sbc8349\0" \ 705 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 706 "nfsroot=${serverip}:${rootpath}\0" \ 707 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 708 "addip=setenv bootargs ${bootargs} " \ 709 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 710 ":${hostname}:${netdev}:off panic=1\0" \ 711 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 712 "flash_nfs=run nfsargs addip addtty;" \ 713 "bootm ${kernel_addr}\0" \ 714 "flash_self=run ramargs addip addtty;" \ 715 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 716 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 717 "bootm\0" \ 718 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 719 "update=protect off fff00000 fff3ffff; " \ 720 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 721 "upd=run load;run update\0" \ 722 "fdtaddr=400000\0" \ 723 "fdtfile=sbc8349.dtb\0" \ 724 "" 725 726 #define CONFIG_NFSBOOTCOMMAND \ 727 "setenv bootargs root=/dev/nfs rw " \ 728 "nfsroot=$serverip:$rootpath " \ 729 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 730 "console=$consoledev,$baudrate $othbootargs;" \ 731 "tftp $loadaddr $bootfile;" \ 732 "tftp $fdtaddr $fdtfile;" \ 733 "bootm $loadaddr - $fdtaddr" 734 735 #define CONFIG_RAMBOOTCOMMAND \ 736 "setenv bootargs root=/dev/ram rw " \ 737 "console=$consoledev,$baudrate $othbootargs;" \ 738 "tftp $ramdiskaddr $ramdiskfile;" \ 739 "tftp $loadaddr $bootfile;" \ 740 "tftp $fdtaddr $fdtfile;" \ 741 "bootm $loadaddr $ramdiskaddr $fdtaddr" 742 743 #define CONFIG_BOOTCOMMAND "run flash_self" 744 745 #endif /* __CONFIG_H */ 746