1927b901bSBo Shen /* 2927b901bSBo Shen * Configuration settings for the SAMA5D4EK board. 3927b901bSBo Shen * 4927b901bSBo Shen * Copyright (C) 2014 Atmel 5927b901bSBo Shen * Bo Shen <voice.shen@atmel.com> 6927b901bSBo Shen * 7927b901bSBo Shen * SPDX-License-Identifier: GPL-2.0+ 8927b901bSBo Shen */ 9927b901bSBo Shen 10927b901bSBo Shen #ifndef __CONFIG_H 11927b901bSBo Shen #define __CONFIG_H 12927b901bSBo Shen 13b2d387bcSWu, Josh #include "at91-sama5_common.h" 14927b901bSBo Shen 15927b901bSBo Shen /* SDRAM */ 16927b901bSBo Shen #define CONFIG_NR_DRAM_BANKS 1 17927b901bSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 18927b901bSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 19927b901bSBo Shen 205a4c9c22SBo Shen #ifdef CONFIG_SPL_BUILD 21*ef33aa3dSWenyou Yang #define CONFIG_SYS_INIT_SP_ADDR 0x218000 225a4c9c22SBo Shen #else 23927b901bSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 24*ef33aa3dSWenyou Yang (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 255a4c9c22SBo Shen #endif 26927b901bSBo Shen 27927b901bSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 28927b901bSBo Shen 29927b901bSBo Shen #ifdef CONFIG_CMD_SF 30927b901bSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 31927b901bSBo Shen #endif 32927b901bSBo Shen 33927b901bSBo Shen /* NAND flash */ 34927b901bSBo Shen #define CONFIG_CMD_NAND 35927b901bSBo Shen 36927b901bSBo Shen #ifdef CONFIG_CMD_NAND 37927b901bSBo Shen #define CONFIG_NAND_ATMEL 38927b901bSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 39927b901bSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 40927b901bSBo Shen /* our ALE is AD21 */ 41927b901bSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 42927b901bSBo Shen /* our CLE is AD22 */ 43927b901bSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 44927b901bSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 45927b901bSBo Shen /* PMECC & PMERRLOC */ 46927b901bSBo Shen #define CONFIG_ATMEL_NAND_HWECC 47927b901bSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 48927b901bSBo Shen #endif 49927b901bSBo Shen 50927b901bSBo Shen /* LCD */ 51927b901bSBo Shen #define LCD_BPP LCD_COLOR16 52927b901bSBo Shen #define LCD_OUTPUT_BPP 18 53927b901bSBo Shen #define CONFIG_LCD_LOGO 54927b901bSBo Shen #define CONFIG_LCD_INFO 55927b901bSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 56927b901bSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 57927b901bSBo Shen #define CONFIG_ATMEL_HLCD 58927b901bSBo Shen #define CONFIG_ATMEL_LCD_RGB565 59927b901bSBo Shen 60927b901bSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 617a53b954SWu, Josh /* override the bootcmd, bootargs and other configuration for spi flash env*/ 62927b901bSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 63dc018fefSWu, Josh /* override the bootcmd, bootargs and other configuration for nandflash env*/ 64927b901bSBo Shen #elif CONFIG_SYS_USE_MMC 65372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 66927b901bSBo Shen #endif 67927b901bSBo Shen 685a4c9c22SBo Shen /* SPL */ 695a4c9c22SBo Shen #define CONFIG_SPL_FRAMEWORK 705a4c9c22SBo Shen #define CONFIG_SPL_TEXT_BASE 0x200000 71*ef33aa3dSWenyou Yang #define CONFIG_SPL_MAX_SIZE 0x18000 725a4c9c22SBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 735a4c9c22SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 745a4c9c22SBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 755a4c9c22SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 765a4c9c22SBo Shen 775a4c9c22SBo Shen #define CONFIG_SPL_BOARD_INIT 785a4c9c22SBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 795a4c9c22SBo Shen 805a4c9c22SBo Shen #ifdef CONFIG_SYS_USE_MMC 81993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds 825a4c9c22SBo Shen #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 835a4c9c22SBo Shen #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 845a4c9c22SBo Shen 855a4c9c22SBo Shen #elif CONFIG_SYS_USE_NANDFLASH 865a4c9c22SBo Shen #define CONFIG_SPL_NAND_DRIVERS 875a4c9c22SBo Shen #define CONFIG_SPL_NAND_BASE 885a4c9c22SBo Shen #define CONFIG_PMECC_CAP 8 895a4c9c22SBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 905a4c9c22SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 915a4c9c22SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 925a4c9c22SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 935a4c9c22SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 945a4c9c22SBo Shen #define CONFIG_SYS_NAND_OOBSIZE 224 955a4c9c22SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 965a4c9c22SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 975a4c9c22SBo Shen #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 985a4c9c22SBo Shen 995a4c9c22SBo Shen #elif CONFIG_SYS_USE_SERIALFLASH 1005a4c9c22SBo Shen #define CONFIG_SPL_SPI_LOAD 101*ef33aa3dSWenyou Yang #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 1025a4c9c22SBo Shen 1035a4c9c22SBo Shen #endif 104927b901bSBo Shen #endif 105