1927b901bSBo Shen /* 2927b901bSBo Shen * Configuration settings for the SAMA5D4EK board. 3927b901bSBo Shen * 4927b901bSBo Shen * Copyright (C) 2014 Atmel 5927b901bSBo Shen * Bo Shen <voice.shen@atmel.com> 6927b901bSBo Shen * 7927b901bSBo Shen * SPDX-License-Identifier: GPL-2.0+ 8927b901bSBo Shen */ 9927b901bSBo Shen 10927b901bSBo Shen #ifndef __CONFIG_H 11927b901bSBo Shen #define __CONFIG_H 12927b901bSBo Shen 13b2d387bcSWu, Josh /* No NOR flash, this definition should put before common header */ 14b2d387bcSWu, Josh #define CONFIG_SYS_NO_FLASH 15927b901bSBo Shen 16b2d387bcSWu, Josh #include "at91-sama5_common.h" 17927b901bSBo Shen 18927b901bSBo Shen /* serial console */ 19927b901bSBo Shen #define CONFIG_ATMEL_USART 20927b901bSBo Shen #define CONFIG_USART_BASE ATMEL_BASE_USART3 21927b901bSBo Shen #define CONFIG_USART_ID ATMEL_ID_USART3 22927b901bSBo Shen 23927b901bSBo Shen /* SDRAM */ 24927b901bSBo Shen #define CONFIG_NR_DRAM_BANKS 1 25927b901bSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 26927b901bSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 27927b901bSBo Shen 285a4c9c22SBo Shen #ifdef CONFIG_SPL_BUILD 295a4c9c22SBo Shen #define CONFIG_SYS_INIT_SP_ADDR 0x210000 305a4c9c22SBo Shen #else 31927b901bSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 32927b901bSBo Shen (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 335a4c9c22SBo Shen #endif 34927b901bSBo Shen 35927b901bSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 36927b901bSBo Shen 37927b901bSBo Shen /* SerialFlash */ 38927b901bSBo Shen #define CONFIG_CMD_SF 39927b901bSBo Shen 40927b901bSBo Shen #ifdef CONFIG_CMD_SF 41927b901bSBo Shen #define CONFIG_ATMEL_SPI 42927b901bSBo Shen #define CONFIG_ATMEL_SPI0 43927b901bSBo Shen #define CONFIG_SPI_FLASH_ATMEL 44927b901bSBo Shen #define CONFIG_SF_DEFAULT_BUS 0 45927b901bSBo Shen #define CONFIG_SF_DEFAULT_CS 0 46927b901bSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 47927b901bSBo Shen #endif 48927b901bSBo Shen 49927b901bSBo Shen /* NAND flash */ 50927b901bSBo Shen #define CONFIG_CMD_NAND 51927b901bSBo Shen 52927b901bSBo Shen #ifdef CONFIG_CMD_NAND 53927b901bSBo Shen #define CONFIG_NAND_ATMEL 54927b901bSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 55927b901bSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 56927b901bSBo Shen /* our ALE is AD21 */ 57927b901bSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 58927b901bSBo Shen /* our CLE is AD22 */ 59927b901bSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 60927b901bSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 61927b901bSBo Shen /* PMECC & PMERRLOC */ 62927b901bSBo Shen #define CONFIG_ATMEL_NAND_HWECC 63927b901bSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 64927b901bSBo Shen #endif 65927b901bSBo Shen 66927b901bSBo Shen /* MMC */ 67927b901bSBo Shen #define CONFIG_CMD_MMC 68927b901bSBo Shen 69927b901bSBo Shen #ifdef CONFIG_CMD_MMC 70927b901bSBo Shen #define CONFIG_MMC 71927b901bSBo Shen #define CONFIG_GENERIC_MMC 72927b901bSBo Shen #define CONFIG_GENERIC_ATMEL_MCI 73927b901bSBo Shen #define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 74927b901bSBo Shen #endif 75927b901bSBo Shen 76927b901bSBo Shen /* USB */ 77927b901bSBo Shen #define CONFIG_CMD_USB 78927b901bSBo Shen 79927b901bSBo Shen #ifdef CONFIG_CMD_USB 80927b901bSBo Shen #define CONFIG_USB_EHCI 81927b901bSBo Shen #define CONFIG_USB_EHCI_ATMEL 82927b901bSBo Shen #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 83927b901bSBo Shen #define CONFIG_USB_STORAGE 84927b901bSBo Shen #endif 85927b901bSBo Shen 86cd5ca303SBo Shen /* USB device */ 87cd5ca303SBo Shen #define CONFIG_USB_GADGET 88cd5ca303SBo Shen #define CONFIG_USB_GADGET_DUALSPEED 89cd5ca303SBo Shen #define CONFIG_USB_GADGET_ATMEL_USBA 90cd5ca303SBo Shen #define CONFIG_USB_ETHER 91cd5ca303SBo Shen #define CONFIG_USB_ETH_RNDIS 92cd5ca303SBo Shen #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" 93cd5ca303SBo Shen 94927b901bSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) 95927b901bSBo Shen #define CONFIG_CMD_FAT 96927b901bSBo Shen #define CONFIG_DOS_PARTITION 97927b901bSBo Shen #endif 98927b901bSBo Shen 99927b901bSBo Shen /* Ethernet Hardware */ 100927b901bSBo Shen #define CONFIG_MACB 101927b901bSBo Shen #define CONFIG_RMII 102927b901bSBo Shen #define CONFIG_NET_RETRY_COUNT 20 103927b901bSBo Shen #define CONFIG_MACB_SEARCH_PHY 104927b901bSBo Shen 105927b901bSBo Shen /* LCD */ 106927b901bSBo Shen #define CONFIG_LCD 107927b901bSBo Shen #define LCD_BPP LCD_COLOR16 108927b901bSBo Shen #define LCD_OUTPUT_BPP 18 109927b901bSBo Shen #define CONFIG_LCD_LOGO 110927b901bSBo Shen #define CONFIG_LCD_INFO 111927b901bSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 112927b901bSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 113927b901bSBo Shen #define CONFIG_ATMEL_HLCD 114927b901bSBo Shen #define CONFIG_ATMEL_LCD_RGB565 115927b901bSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV 116927b901bSBo Shen 117927b901bSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 118927b901bSBo Shen /* bootstrap + u-boot + env + linux in serial flash */ 119927b901bSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH 120927b901bSBo Shen #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 121927b901bSBo Shen #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 122927b901bSBo Shen #define CONFIG_ENV_OFFSET 0x10000 123927b901bSBo Shen #define CONFIG_ENV_SIZE 0x10000 124927b901bSBo Shen #define CONFIG_ENV_SECT_SIZE 0x1000 125927b901bSBo Shen #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 126927b901bSBo Shen "sf read 0x21000000 0xa0000 0x60000; " \ 127927b901bSBo Shen "sf read 0x22000000 0x100000 0x300000; " \ 128927b901bSBo Shen "bootz 0x22000000 - 0x21000000" 129927b901bSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 130*dc018fefSWu, Josh /* override the bootcmd, bootargs and other configuration for nandflash env*/ 131927b901bSBo Shen #elif CONFIG_SYS_USE_MMC 132372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 133927b901bSBo Shen #endif 134927b901bSBo Shen 1355a4c9c22SBo Shen /* SPL */ 1365a4c9c22SBo Shen #define CONFIG_SPL_FRAMEWORK 1375a4c9c22SBo Shen #define CONFIG_SPL_TEXT_BASE 0x200000 1385a4c9c22SBo Shen #define CONFIG_SPL_MAX_SIZE 0x10000 1395a4c9c22SBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 1405a4c9c22SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 1415a4c9c22SBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 1425a4c9c22SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 1435a4c9c22SBo Shen 1445a4c9c22SBo Shen #define CONFIG_SPL_LIBCOMMON_SUPPORT 1455a4c9c22SBo Shen #define CONFIG_SPL_LIBGENERIC_SUPPORT 1465a4c9c22SBo Shen #define CONFIG_SPL_GPIO_SUPPORT 1475a4c9c22SBo Shen #define CONFIG_SPL_SERIAL_SUPPORT 1485a4c9c22SBo Shen 1495a4c9c22SBo Shen #define CONFIG_SPL_BOARD_INIT 1505a4c9c22SBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 1515a4c9c22SBo Shen 1525a4c9c22SBo Shen #ifdef CONFIG_SYS_USE_MMC 153993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds 1545a4c9c22SBo Shen #define CONFIG_SPL_MMC_SUPPORT 1555a4c9c22SBo Shen #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 1565a4c9c22SBo Shen #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 1575a4c9c22SBo Shen #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 1585a4c9c22SBo Shen #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 1595a4c9c22SBo Shen #define CONFIG_SPL_FAT_SUPPORT 1605a4c9c22SBo Shen #define CONFIG_SPL_LIBDISK_SUPPORT 1615a4c9c22SBo Shen 1625a4c9c22SBo Shen #elif CONFIG_SYS_USE_NANDFLASH 1635a4c9c22SBo Shen #define CONFIG_SPL_NAND_SUPPORT 1645a4c9c22SBo Shen #define CONFIG_SPL_NAND_DRIVERS 1655a4c9c22SBo Shen #define CONFIG_SPL_NAND_BASE 1665a4c9c22SBo Shen #define CONFIG_PMECC_CAP 8 1675a4c9c22SBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 1685a4c9c22SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 1695a4c9c22SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 1705a4c9c22SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 1715a4c9c22SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 1725a4c9c22SBo Shen #define CONFIG_SYS_NAND_OOBSIZE 224 1735a4c9c22SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 1745a4c9c22SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 1755a4c9c22SBo Shen #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 1765a4c9c22SBo Shen 1775a4c9c22SBo Shen #elif CONFIG_SYS_USE_SERIALFLASH 1785a4c9c22SBo Shen #define CONFIG_SPL_SPI_SUPPORT 1795a4c9c22SBo Shen #define CONFIG_SPL_SPI_FLASH_SUPPORT 1805a4c9c22SBo Shen #define CONFIG_SPL_SPI_LOAD 1815a4c9c22SBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 1825a4c9c22SBo Shen 1835a4c9c22SBo Shen #endif 184927b901bSBo Shen #endif 185