1f196044dSBo Shen /* 2f196044dSBo Shen * Configuration settings for the SAMA5D4 Xplained ultra board. 3f196044dSBo Shen * 4f196044dSBo Shen * Copyright (C) 2014 Atmel 5f196044dSBo Shen * Bo Shen <voice.shen@atmel.com> 6f196044dSBo Shen * 7f196044dSBo Shen * SPDX-License-Identifier: GPL-2.0+ 8f196044dSBo Shen */ 9f196044dSBo Shen 10f196044dSBo Shen #ifndef __CONFIG_H 11f196044dSBo Shen #define __CONFIG_H 12f196044dSBo Shen 13b2d387bcSWu, Josh #include "at91-sama5_common.h" 14f196044dSBo Shen 15f196044dSBo Shen /* SDRAM */ 16f196044dSBo Shen #define CONFIG_NR_DRAM_BANKS 1 17f196044dSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 18f196044dSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 19f196044dSBo Shen 200b2a9824SBo Shen #ifdef CONFIG_SPL_BUILD 21*6dbadb4dSWenyou Yang #define CONFIG_SYS_INIT_SP_ADDR 0x218000 220b2a9824SBo Shen #else 23f196044dSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 24*6dbadb4dSWenyou Yang (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 250b2a9824SBo Shen #endif 26f196044dSBo Shen 27f196044dSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 28f196044dSBo Shen 29f196044dSBo Shen #ifdef CONFIG_CMD_SF 30f196044dSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 31f196044dSBo Shen #endif 32f196044dSBo Shen 33f196044dSBo Shen /* NAND flash */ 34f196044dSBo Shen #define CONFIG_CMD_NAND 35f196044dSBo Shen 36f196044dSBo Shen #ifdef CONFIG_CMD_NAND 37f196044dSBo Shen #define CONFIG_NAND_ATMEL 38f196044dSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 39f196044dSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 40f196044dSBo Shen /* our ALE is AD21 */ 41f196044dSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 42f196044dSBo Shen /* our CLE is AD22 */ 43f196044dSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 44f196044dSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 45f196044dSBo Shen /* PMECC & PMERRLOC */ 46f196044dSBo Shen #define CONFIG_ATMEL_NAND_HWECC 47f196044dSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 48f196044dSBo Shen #endif 49f196044dSBo Shen 50f196044dSBo Shen /* LCD */ 51f196044dSBo Shen #ifdef CONFIG_LCD 52f196044dSBo Shen #define LCD_BPP LCD_COLOR16 53f196044dSBo Shen #define LCD_OUTPUT_BPP 24 54f196044dSBo Shen #define CONFIG_LCD_LOGO 55f196044dSBo Shen #define CONFIG_LCD_INFO 56f196044dSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 57f196044dSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 58f196044dSBo Shen #define CONFIG_ATMEL_HLCD 59f196044dSBo Shen #define CONFIG_ATMEL_LCD_RGB565 60f196044dSBo Shen #endif 61f196044dSBo Shen 62f196044dSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 637a53b954SWu, Josh /* override the bootcmd, bootargs and other configuration for spi flash env */ 64f196044dSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 65dc018fefSWu, Josh /* override the bootcmd, bootargs and other configuration for nandflash env */ 66f196044dSBo Shen #elif CONFIG_SYS_USE_MMC 67372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 68f196044dSBo Shen #endif 69f196044dSBo Shen 700b2a9824SBo Shen /* SPL */ 710b2a9824SBo Shen #define CONFIG_SPL_FRAMEWORK 720b2a9824SBo Shen #define CONFIG_SPL_TEXT_BASE 0x200000 73*6dbadb4dSWenyou Yang #define CONFIG_SPL_MAX_SIZE 0x18000 740b2a9824SBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 750b2a9824SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 760b2a9824SBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 770b2a9824SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 780b2a9824SBo Shen 790b2a9824SBo Shen #define CONFIG_SPL_BOARD_INIT 800b2a9824SBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 810b2a9824SBo Shen 820b2a9824SBo Shen #ifdef CONFIG_SYS_USE_MMC 83993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds 840b2a9824SBo Shen #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 850b2a9824SBo Shen #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 860b2a9824SBo Shen 870b2a9824SBo Shen #elif CONFIG_SYS_USE_NANDFLASH 880b2a9824SBo Shen #define CONFIG_SPL_NAND_DRIVERS 890b2a9824SBo Shen #define CONFIG_SPL_NAND_BASE 900b2a9824SBo Shen #define CONFIG_PMECC_CAP 8 910b2a9824SBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 920b2a9824SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 930b2a9824SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 940b2a9824SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 950b2a9824SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 960b2a9824SBo Shen #define CONFIG_SYS_NAND_OOBSIZE 224 970b2a9824SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 980b2a9824SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 990b2a9824SBo Shen #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 1000b2a9824SBo Shen 1010b2a9824SBo Shen #elif CONFIG_SYS_USE_SERIALFLASH 1020b2a9824SBo Shen #define CONFIG_SPL_SPI_LOAD 103*6dbadb4dSWenyou Yang #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 1040b2a9824SBo Shen 1050b2a9824SBo Shen #endif 106f196044dSBo Shen #endif 107