13225f34eSBo Shen /* 23225f34eSBo Shen * Configuation settings for the SAMA5D3xEK board. 33225f34eSBo Shen * 43225f34eSBo Shen * Copyright (C) 2012 - 2013 Atmel 53225f34eSBo Shen * 63225f34eSBo Shen * based on at91sam9m10g45ek.h by: 73225f34eSBo Shen * Stelian Pop <stelian@popies.net> 83225f34eSBo Shen * Lead Tech Design <www.leadtechdesign.com> 93225f34eSBo Shen * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 113225f34eSBo Shen */ 123225f34eSBo Shen 133225f34eSBo Shen #ifndef __CONFIG_H 143225f34eSBo Shen #define __CONFIG_H 153225f34eSBo Shen 163225f34eSBo Shen #include <asm/hardware.h> 173225f34eSBo Shen 183225f34eSBo Shen #define CONFIG_SYS_TEXT_BASE 0x26f00000 193225f34eSBo Shen 203225f34eSBo Shen /* ARM asynchronous clock */ 213225f34eSBo Shen #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 223225f34eSBo Shen #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 233225f34eSBo Shen #define CONFIG_SYS_HZ 1000 243225f34eSBo Shen 253225f34eSBo Shen #define CONFIG_AT91FAMILY 263225f34eSBo Shen #define CONFIG_ARCH_CPU_INIT 273225f34eSBo Shen 283225f34eSBo Shen #define CONFIG_SKIP_LOWLEVEL_INIT 293225f34eSBo Shen #define CONFIG_BOARD_EARLY_INIT_F 303225f34eSBo Shen #define CONFIG_DISPLAY_CPUINFO 313225f34eSBo Shen 323225f34eSBo Shen #define CONFIG_CMD_BOOTZ 333225f34eSBo Shen #define CONFIG_OF_LIBFDT /* Device Tree support */ 343225f34eSBo Shen 353225f34eSBo Shen /* general purpose I/O */ 363225f34eSBo Shen #define CONFIG_AT91_GPIO 373225f34eSBo Shen 383225f34eSBo Shen /* serial console */ 393225f34eSBo Shen #define CONFIG_ATMEL_USART 403225f34eSBo Shen #define CONFIG_USART_BASE ATMEL_BASE_DBGU 413225f34eSBo Shen #define CONFIG_USART_ID ATMEL_ID_DBGU 423225f34eSBo Shen 433225f34eSBo Shen /* 443225f34eSBo Shen * This needs to be defined for the OHCI code to work but it is defined as 453225f34eSBo Shen * ATMEL_ID_UHPHS in the CPU specific header files. 463225f34eSBo Shen */ 473225f34eSBo Shen #define ATMEL_ID_UHP ATMEL_ID_UHPHS 483225f34eSBo Shen 493225f34eSBo Shen /* 503225f34eSBo Shen * Specify the clock enable bit in the PMC_SCER register. 513225f34eSBo Shen */ 523225f34eSBo Shen #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 533225f34eSBo Shen 543225f34eSBo Shen /* LCD */ 553225f34eSBo Shen #define CONFIG_LCD 563225f34eSBo Shen #define LCD_BPP LCD_COLOR16 573225f34eSBo Shen #define LCD_OUTPUT_BPP 24 583225f34eSBo Shen #define CONFIG_LCD_LOGO 593225f34eSBo Shen #undef LCD_TEST_PATTERN 603225f34eSBo Shen #define CONFIG_LCD_INFO 613225f34eSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 623225f34eSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 633225f34eSBo Shen #define CONFIG_ATMEL_HLCD 643225f34eSBo Shen #define CONFIG_ATMEL_LCD_RGB565 653225f34eSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV 663225f34eSBo Shen 673225f34eSBo Shen /* board specific (not enough SRAM) */ 683225f34eSBo Shen #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 693225f34eSBo Shen 703225f34eSBo Shen #define CONFIG_BOOTDELAY 3 713225f34eSBo Shen 723225f34eSBo Shen /* 733225f34eSBo Shen * BOOTP options 743225f34eSBo Shen */ 753225f34eSBo Shen #define CONFIG_BOOTP_BOOTFILESIZE 763225f34eSBo Shen #define CONFIG_BOOTP_BOOTPATH 773225f34eSBo Shen #define CONFIG_BOOTP_GATEWAY 783225f34eSBo Shen #define CONFIG_BOOTP_HOSTNAME 793225f34eSBo Shen 803225f34eSBo Shen /* No NOR flash */ 813225f34eSBo Shen #define CONFIG_SYS_NO_FLASH 823225f34eSBo Shen 833225f34eSBo Shen /* 843225f34eSBo Shen * Command line configuration. 853225f34eSBo Shen */ 863225f34eSBo Shen #include <config_cmd_default.h> 873225f34eSBo Shen #undef CONFIG_CMD_FPGA 883225f34eSBo Shen #undef CONFIG_CMD_IMI 893225f34eSBo Shen #undef CONFIG_CMD_LOADS 903225f34eSBo Shen #define CONFIG_CMD_PING 913225f34eSBo Shen #define CONFIG_CMD_DHCP 923225f34eSBo Shen 933225f34eSBo Shen /* SDRAM */ 943225f34eSBo Shen #define CONFIG_NR_DRAM_BANKS 1 953225f34eSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 963225f34eSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 973225f34eSBo Shen 983225f34eSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 993225f34eSBo Shen (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 1003225f34eSBo Shen 1013225f34eSBo Shen /* SerialFlash */ 1023225f34eSBo Shen #define CONFIG_CMD_SF 1033225f34eSBo Shen 1043225f34eSBo Shen #ifdef CONFIG_CMD_SF 1053225f34eSBo Shen #define CONFIG_ATMEL_SPI 1063225f34eSBo Shen #define CONFIG_SPI_FLASH 1073225f34eSBo Shen #define CONFIG_SPI_FLASH_ATMEL 1083225f34eSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 1093225f34eSBo Shen #endif 1103225f34eSBo Shen 1113225f34eSBo Shen /* NAND flash */ 1123225f34eSBo Shen #define CONFIG_CMD_NAND 1133225f34eSBo Shen 1143225f34eSBo Shen #ifdef CONFIG_CMD_NAND 1153225f34eSBo Shen #define CONFIG_NAND_MAX_CHIPS 1 1163225f34eSBo Shen #define CONFIG_NAND_ATMEL 1173225f34eSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 1183225f34eSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 1193225f34eSBo Shen /* our ALE is AD21 */ 1203225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 1213225f34eSBo Shen /* our CLE is AD22 */ 1223225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 1233225f34eSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 1243225f34eSBo Shen /* PMECC & PMERRLOC */ 1253225f34eSBo Shen #define CONFIG_ATMEL_NAND_HWECC 1263225f34eSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 1273225f34eSBo Shen #define CONFIG_PMECC_CAP 4 1283225f34eSBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 1293225f34eSBo Shen #define CONFIG_PMECC_INDEX_TABLE_OFFSET ATMEL_PMECC_INDEX_OFFSET_512 1303225f34eSBo Shen #define CONFIG_CMD_NAND_TRIMFFS 1313225f34eSBo Shen #endif 1323225f34eSBo Shen 1333225f34eSBo Shen /* Ethernet Hardware */ 1343225f34eSBo Shen #define CONFIG_MACB 1353225f34eSBo Shen #define CONFIG_RMII 1363225f34eSBo Shen #define CONFIG_NET_MULTI 1373225f34eSBo Shen #define CONFIG_NET_RETRY_COUNT 20 1383225f34eSBo Shen #define CONFIG_MACB_SEARCH_PHY 139*e08d6f3aSBo Shen #define CONFIG_RGMII 140*e08d6f3aSBo Shen #define CONFIG_CMD_MII 141*e08d6f3aSBo Shen #define CONFIG_PHYLIB 142*e08d6f3aSBo Shen #define CONFIG_PHY_MICREL 143*e08d6f3aSBo Shen #define CONFIG_PHY_MICREL_KSZ9021 1443225f34eSBo Shen 1453225f34eSBo Shen /* MMC */ 1463225f34eSBo Shen #define CONFIG_CMD_MMC 1473225f34eSBo Shen 1483225f34eSBo Shen #ifdef CONFIG_CMD_MMC 1493225f34eSBo Shen #define CONFIG_MMC 1503225f34eSBo Shen #define CONFIG_GENERIC_MMC 1513225f34eSBo Shen #define CONFIG_GENERIC_ATMEL_MCI 1523225f34eSBo Shen #define ATMEL_BASE_MMCI ATMEL_BASE_MCI0 1533225f34eSBo Shen #endif 1543225f34eSBo Shen 1553225f34eSBo Shen /* USB */ 1563225f34eSBo Shen #define CONFIG_CMD_USB 1573225f34eSBo Shen 1583225f34eSBo Shen #ifdef CONFIG_CMD_USB 1593225f34eSBo Shen #define CONFIG_USB_ATMEL 1603225f34eSBo Shen #define CONFIG_USB_OHCI_NEW 1613225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT 1623225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 1633225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" 1643225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 1653225f34eSBo Shen #define CONFIG_DOS_PARTITION 1663225f34eSBo Shen #define CONFIG_USB_STORAGE 1673225f34eSBo Shen #endif 1683225f34eSBo Shen 1693225f34eSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) 1703225f34eSBo Shen #define CONFIG_CMD_FAT 1713225f34eSBo Shen #endif 1723225f34eSBo Shen 1733225f34eSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 1743225f34eSBo Shen 1753225f34eSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 1763225f34eSBo Shen /* bootstrap + u-boot + env + linux in serial flash */ 1773225f34eSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH 1783225f34eSBo Shen #define CONFIG_ENV_OFFSET 0x5000 1793225f34eSBo Shen #define CONFIG_ENV_SIZE 0x3000 1803225f34eSBo Shen #define CONFIG_ENV_SECT_SIZE 0x1000 1813225f34eSBo Shen #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 1823225f34eSBo Shen "sf read 0x22000000 0x42000 0x300000; " \ 1833225f34eSBo Shen "bootm 0x22000000" 1843225f34eSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 1853225f34eSBo Shen /* bootstrap + u-boot + env in nandflash */ 1863225f34eSBo Shen #define CONFIG_ENV_IS_IN_NAND 1873225f34eSBo Shen #define CONFIG_ENV_OFFSET 0xc0000 1883225f34eSBo Shen #define CONFIG_ENV_OFFSET_REDUND 0x100000 1893225f34eSBo Shen #define CONFIG_ENV_SIZE 0x20000 1903225f34eSBo Shen #define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ 1913225f34eSBo Shen "nand read 0x22000000 0x200000 0x600000;" \ 1923225f34eSBo Shen "bootm 0x22000000 - 0x21000000" 1933225f34eSBo Shen #elif CONFIG_SYS_USE_MMC 1943225f34eSBo Shen /* bootstrap + u-boot + env in sd card */ 1953225f34eSBo Shen #define CONFIG_ENV_IS_IN_MMC 1963225f34eSBo Shen #define CONFIG_ENV_OFFSET 0x2000 1973225f34eSBo Shen #define CONFIG_ENV_SIZE 0x1000 1983225f34eSBo Shen #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ 1993225f34eSBo Shen "fatload mmc 0:1 0x22000000 uImage; " \ 2003225f34eSBo Shen "bootm 0x22000000 - 0x21000000" 2013225f34eSBo Shen #define CONFIG_SYS_MMC_ENV_DEV 0 2023225f34eSBo Shen #else 2033225f34eSBo Shen #define CONIG_ENV_IS_NOWHERE 2043225f34eSBo Shen #endif 2053225f34eSBo Shen 2063225f34eSBo Shen #ifdef CONFIG_SYS_USE_MMC 2073225f34eSBo Shen #define CONFIG_BOOTARGS \ 2083225f34eSBo Shen "console=ttyS0,115200 earlyprintk " \ 2093225f34eSBo Shen "root=/dev/mmcblk0p2 rw rootwait" 2103225f34eSBo Shen #else 2113225f34eSBo Shen #define CONFIG_BOOTARGS \ 2123225f34eSBo Shen "console=ttyS0,115200 earlyprintk " \ 2133225f34eSBo Shen "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 2143225f34eSBo Shen "256K(env),256k(evn_redundent),256k(spare)," \ 2153225f34eSBo Shen "512k(dtb),6M(kernel)ro,-(rootfs) " \ 2163225f34eSBo Shen "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" 2173225f34eSBo Shen #endif 2183225f34eSBo Shen 2193225f34eSBo Shen #define CONFIG_BAUDRATE 115200 2203225f34eSBo Shen 2213225f34eSBo Shen #define CONFIG_SYS_PROMPT "U-Boot> " 2223225f34eSBo Shen #define CONFIG_SYS_CBSIZE 256 2233225f34eSBo Shen #define CONFIG_SYS_MAXARGS 16 2243225f34eSBo Shen #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 2253225f34eSBo Shen sizeof(CONFIG_SYS_PROMPT) + 16) 2263225f34eSBo Shen #define CONFIG_SYS_LONGHELP 2273225f34eSBo Shen #define CONFIG_CMDLINE_EDITING 2283225f34eSBo Shen #define CONFIG_AUTO_COMPLETE 2293225f34eSBo Shen #define CONFIG_SYS_HUSH_PARSER 2303225f34eSBo Shen 2313225f34eSBo Shen /* Size of malloc() pool */ 2323225f34eSBo Shen #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 2333225f34eSBo Shen 2343225f34eSBo Shen #endif 235