13225f34eSBo Shen /* 23225f34eSBo Shen * Configuation settings for the SAMA5D3xEK board. 33225f34eSBo Shen * 43225f34eSBo Shen * Copyright (C) 2012 - 2013 Atmel 53225f34eSBo Shen * 63225f34eSBo Shen * based on at91sam9m10g45ek.h by: 73225f34eSBo Shen * Stelian Pop <stelian@popies.net> 83225f34eSBo Shen * Lead Tech Design <www.leadtechdesign.com> 93225f34eSBo Shen * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 113225f34eSBo Shen */ 123225f34eSBo Shen 133225f34eSBo Shen #ifndef __CONFIG_H 143225f34eSBo Shen #define __CONFIG_H 153225f34eSBo Shen 16b2d387bcSWu, Josh /* 17b2d387bcSWu, Josh * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH 18b2d387bcSWu, Josh * before the common header. 19b2d387bcSWu, Josh */ 20b2d387bcSWu, Josh #include "at91-sama5_common.h" 213225f34eSBo Shen 2289a3658aSWu, Josh #define CONFIG_BOARD_LATE_INIT 2389a3658aSWu, Josh #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 2489a3658aSWu, Josh 253225f34eSBo Shen /* serial console */ 263225f34eSBo Shen #define CONFIG_ATMEL_USART 273225f34eSBo Shen #define CONFIG_USART_BASE ATMEL_BASE_DBGU 283225f34eSBo Shen #define CONFIG_USART_ID ATMEL_ID_DBGU 293225f34eSBo Shen 303225f34eSBo Shen /* 313225f34eSBo Shen * This needs to be defined for the OHCI code to work but it is defined as 323225f34eSBo Shen * ATMEL_ID_UHPHS in the CPU specific header files. 333225f34eSBo Shen */ 343225f34eSBo Shen #define ATMEL_ID_UHP ATMEL_ID_UHPHS 353225f34eSBo Shen 363225f34eSBo Shen /* 373225f34eSBo Shen * Specify the clock enable bit in the PMC_SCER register. 383225f34eSBo Shen */ 393225f34eSBo Shen #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 403225f34eSBo Shen 413225f34eSBo Shen /* LCD */ 423225f34eSBo Shen #define CONFIG_LCD 433225f34eSBo Shen #define LCD_BPP LCD_COLOR16 443225f34eSBo Shen #define LCD_OUTPUT_BPP 24 453225f34eSBo Shen #define CONFIG_LCD_LOGO 463225f34eSBo Shen #define CONFIG_LCD_INFO 473225f34eSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 483225f34eSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 493225f34eSBo Shen #define CONFIG_ATMEL_HLCD 503225f34eSBo Shen #define CONFIG_ATMEL_LCD_RGB565 513225f34eSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV 523225f34eSBo Shen 533225f34eSBo Shen /* board specific (not enough SRAM) */ 543225f34eSBo Shen #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 553225f34eSBo Shen 56d6b79434SBo Shen /* NOR flash */ 57b2d387bcSWu, Josh #ifndef CONFIG_SYS_NO_FLASH 58d6b79434SBo Shen #define CONFIG_FLASH_CFI_DRIVER 59d6b79434SBo Shen #define CONFIG_SYS_FLASH_CFI 60d6b79434SBo Shen #define CONFIG_SYS_FLASH_PROTECTION 61d6b79434SBo Shen #define CONFIG_SYS_FLASH_BASE 0x10000000 62d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_SECT 131 63d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_BANKS 1 64d6b79434SBo Shen #endif 653225f34eSBo Shen 663225f34eSBo Shen /* SDRAM */ 673225f34eSBo Shen #define CONFIG_NR_DRAM_BANKS 1 683225f34eSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 693225f34eSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 703225f34eSBo Shen 71c5e8885aSBo Shen #ifdef CONFIG_SPL_BUILD 72c5e8885aSBo Shen #define CONFIG_SYS_INIT_SP_ADDR 0x310000 73c5e8885aSBo Shen #else 743225f34eSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 753225f34eSBo Shen (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 76c5e8885aSBo Shen #endif 773225f34eSBo Shen 783225f34eSBo Shen /* SerialFlash */ 793225f34eSBo Shen #define CONFIG_CMD_SF 803225f34eSBo Shen 813225f34eSBo Shen #ifdef CONFIG_CMD_SF 823225f34eSBo Shen #define CONFIG_ATMEL_SPI 833225f34eSBo Shen #define CONFIG_SPI_FLASH_ATMEL 843225f34eSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 853225f34eSBo Shen #endif 863225f34eSBo Shen 873225f34eSBo Shen /* NAND flash */ 883225f34eSBo Shen #define CONFIG_CMD_NAND 893225f34eSBo Shen 903225f34eSBo Shen #ifdef CONFIG_CMD_NAND 913225f34eSBo Shen #define CONFIG_NAND_ATMEL 923225f34eSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 933225f34eSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 943225f34eSBo Shen /* our ALE is AD21 */ 953225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 963225f34eSBo Shen /* our CLE is AD22 */ 973225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 983225f34eSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 993225f34eSBo Shen /* PMECC & PMERRLOC */ 1003225f34eSBo Shen #define CONFIG_ATMEL_NAND_HWECC 1013225f34eSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 1023225f34eSBo Shen #define CONFIG_PMECC_CAP 4 1033225f34eSBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 1043225f34eSBo Shen #define CONFIG_CMD_NAND_TRIMFFS 1053225f34eSBo Shen #endif 1063225f34eSBo Shen 1073225f34eSBo Shen /* Ethernet Hardware */ 1083225f34eSBo Shen #define CONFIG_MACB 1093225f34eSBo Shen #define CONFIG_RMII 1103225f34eSBo Shen #define CONFIG_NET_RETRY_COUNT 20 1113225f34eSBo Shen #define CONFIG_MACB_SEARCH_PHY 112e08d6f3aSBo Shen #define CONFIG_RGMII 113e08d6f3aSBo Shen #define CONFIG_CMD_MII 114e08d6f3aSBo Shen #define CONFIG_PHYLIB 115e08d6f3aSBo Shen #define CONFIG_PHY_MICREL 116e08d6f3aSBo Shen #define CONFIG_PHY_MICREL_KSZ9021 1173225f34eSBo Shen 1183225f34eSBo Shen /* MMC */ 1193225f34eSBo Shen #define CONFIG_CMD_MMC 1203225f34eSBo Shen 1213225f34eSBo Shen #ifdef CONFIG_CMD_MMC 1223225f34eSBo Shen #define CONFIG_MMC 1233225f34eSBo Shen #define CONFIG_GENERIC_MMC 1243225f34eSBo Shen #define CONFIG_GENERIC_ATMEL_MCI 1253225f34eSBo Shen #define ATMEL_BASE_MMCI ATMEL_BASE_MCI0 1263225f34eSBo Shen #endif 1273225f34eSBo Shen 1283225f34eSBo Shen /* USB */ 1293225f34eSBo Shen #define CONFIG_CMD_USB 1303225f34eSBo Shen 1313225f34eSBo Shen #ifdef CONFIG_CMD_USB 1323225f34eSBo Shen #define CONFIG_USB_ATMEL 133dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 1343225f34eSBo Shen #define CONFIG_USB_OHCI_NEW 1353225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT 1363225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 1373225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" 1383225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 1393225f34eSBo Shen #define CONFIG_DOS_PARTITION 1403225f34eSBo Shen #define CONFIG_USB_STORAGE 1413225f34eSBo Shen #endif 1423225f34eSBo Shen 1433668ce3cSBo Shen /* USB device */ 1443668ce3cSBo Shen #define CONFIG_USB_GADGET 1453668ce3cSBo Shen #define CONFIG_USB_GADGET_DUALSPEED 1463668ce3cSBo Shen #define CONFIG_USB_GADGET_ATMEL_USBA 1473668ce3cSBo Shen #define CONFIG_USB_ETHER 1483668ce3cSBo Shen #define CONFIG_USB_ETH_RNDIS 1493668ce3cSBo Shen #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" 1503668ce3cSBo Shen 1513225f34eSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) 1523225f34eSBo Shen #define CONFIG_CMD_FAT 153a248558aSWu, Josh #define CONFIG_FAT_WRITE 1543225f34eSBo Shen #endif 1553225f34eSBo Shen 1563225f34eSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 1573225f34eSBo Shen 1583225f34eSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 1593225f34eSBo Shen /* bootstrap + u-boot + env + linux in serial flash */ 1603225f34eSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH 1613225f34eSBo Shen #define CONFIG_ENV_OFFSET 0x5000 1623225f34eSBo Shen #define CONFIG_ENV_SIZE 0x3000 1633225f34eSBo Shen #define CONFIG_ENV_SECT_SIZE 0x1000 1643225f34eSBo Shen #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 1653225f34eSBo Shen "sf read 0x22000000 0x42000 0x300000; " \ 1663225f34eSBo Shen "bootm 0x22000000" 1673225f34eSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 168*dc018fefSWu, Josh /* override the bootcmd, bootargs and other configuration nandflash env */ 1693225f34eSBo Shen #elif CONFIG_SYS_USE_MMC 170372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 1713225f34eSBo Shen #else 172a4c79b3aSBo Shen #define CONFIG_ENV_IS_NOWHERE 1733225f34eSBo Shen #endif 1743225f34eSBo Shen 175c5e8885aSBo Shen /* SPL */ 176c5e8885aSBo Shen #define CONFIG_SPL_FRAMEWORK 177c5e8885aSBo Shen #define CONFIG_SPL_TEXT_BASE 0x300000 178c5e8885aSBo Shen #define CONFIG_SPL_MAX_SIZE 0x10000 179c5e8885aSBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 180c5e8885aSBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 181c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 182c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 183c5e8885aSBo Shen 184c5e8885aSBo Shen #define CONFIG_SPL_LIBCOMMON_SUPPORT 185c5e8885aSBo Shen #define CONFIG_SPL_LIBGENERIC_SUPPORT 186c5e8885aSBo Shen #define CONFIG_SPL_GPIO_SUPPORT 187c5e8885aSBo Shen #define CONFIG_SPL_SERIAL_SUPPORT 188c5e8885aSBo Shen 189c5e8885aSBo Shen #define CONFIG_SPL_BOARD_INIT 1908a45b0baSBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 1918a45b0baSBo Shen 192c5e8885aSBo Shen #ifdef CONFIG_SYS_USE_MMC 193993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds 194c5e8885aSBo Shen #define CONFIG_SPL_MMC_SUPPORT 195c5e8885aSBo Shen #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 196c5e8885aSBo Shen #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 197e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 198205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 199c5e8885aSBo Shen #define CONFIG_SPL_FAT_SUPPORT 200c5e8885aSBo Shen #define CONFIG_SPL_LIBDISK_SUPPORT 2018a45b0baSBo Shen 20227019e4aSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 20327019e4aSBo Shen #define CONFIG_SPL_NAND_SUPPORT 20427019e4aSBo Shen #define CONFIG_SPL_NAND_DRIVERS 20527019e4aSBo Shen #define CONFIG_SPL_NAND_BASE 20627019e4aSBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 20727019e4aSBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 20827019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 20927019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 21027019e4aSBo Shen #define CONFIG_SYS_NAND_OOBSIZE 64 21127019e4aSBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 21227019e4aSBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 213e166a831SAndreas Bießmann #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 21427019e4aSBo Shen 2158a45b0baSBo Shen #elif CONFIG_SYS_USE_SERIALFLASH 2168a45b0baSBo Shen #define CONFIG_SPL_SPI_SUPPORT 2178a45b0baSBo Shen #define CONFIG_SPL_SPI_FLASH_SUPPORT 2188a45b0baSBo Shen #define CONFIG_SPL_SPI_LOAD 2198a45b0baSBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 2208a45b0baSBo Shen 221c5e8885aSBo Shen #endif 222c5e8885aSBo Shen 2233225f34eSBo Shen #endif 224