xref: /rk3399_rockchip-uboot/include/configs/sama5d3xek.h (revision b2d387bcebba352ca64b781486507800964d7ffd)
13225f34eSBo Shen /*
23225f34eSBo Shen  * Configuation settings for the SAMA5D3xEK board.
33225f34eSBo Shen  *
43225f34eSBo Shen  * Copyright (C) 2012 - 2013 Atmel
53225f34eSBo Shen  *
63225f34eSBo Shen  * based on at91sam9m10g45ek.h by:
73225f34eSBo Shen  * Stelian Pop <stelian@popies.net>
83225f34eSBo Shen  * Lead Tech Design <www.leadtechdesign.com>
93225f34eSBo Shen  *
101a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
113225f34eSBo Shen  */
123225f34eSBo Shen 
133225f34eSBo Shen #ifndef __CONFIG_H
143225f34eSBo Shen #define __CONFIG_H
153225f34eSBo Shen 
16*b2d387bcSWu, Josh /*
17*b2d387bcSWu, Josh  * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
18*b2d387bcSWu, Josh  * before the common header.
19*b2d387bcSWu, Josh  */
20*b2d387bcSWu, Josh #include "at91-sama5_common.h"
213225f34eSBo Shen 
223225f34eSBo Shen /* serial console */
233225f34eSBo Shen #define CONFIG_ATMEL_USART
243225f34eSBo Shen #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
253225f34eSBo Shen #define	CONFIG_USART_ID			ATMEL_ID_DBGU
263225f34eSBo Shen 
273225f34eSBo Shen /*
283225f34eSBo Shen  * This needs to be defined for the OHCI code to work but it is defined as
293225f34eSBo Shen  * ATMEL_ID_UHPHS in the CPU specific header files.
303225f34eSBo Shen  */
313225f34eSBo Shen #define ATMEL_ID_UHP			ATMEL_ID_UHPHS
323225f34eSBo Shen 
333225f34eSBo Shen /*
343225f34eSBo Shen  * Specify the clock enable bit in the PMC_SCER register.
353225f34eSBo Shen  */
363225f34eSBo Shen #define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
373225f34eSBo Shen 
383225f34eSBo Shen /* LCD */
393225f34eSBo Shen #define CONFIG_LCD
403225f34eSBo Shen #define LCD_BPP				LCD_COLOR16
413225f34eSBo Shen #define LCD_OUTPUT_BPP                  24
423225f34eSBo Shen #define CONFIG_LCD_LOGO
433225f34eSBo Shen #define CONFIG_LCD_INFO
443225f34eSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO
453225f34eSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK
463225f34eSBo Shen #define CONFIG_ATMEL_HLCD
473225f34eSBo Shen #define CONFIG_ATMEL_LCD_RGB565
483225f34eSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV
493225f34eSBo Shen 
503225f34eSBo Shen /* board specific (not enough SRAM) */
513225f34eSBo Shen #define CONFIG_SAMA5D3_LCD_BASE		0x23E00000
523225f34eSBo Shen 
53d6b79434SBo Shen /* NOR flash */
54*b2d387bcSWu, Josh #ifndef CONFIG_SYS_NO_FLASH
55d6b79434SBo Shen #define CONFIG_CMD_FLASH
56d6b79434SBo Shen #define CONFIG_FLASH_CFI_DRIVER
57d6b79434SBo Shen #define CONFIG_SYS_FLASH_CFI
58d6b79434SBo Shen #define CONFIG_SYS_FLASH_PROTECTION
59d6b79434SBo Shen #define CONFIG_SYS_FLASH_BASE		0x10000000
60d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_SECT	131
61d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_BANKS	1
62d6b79434SBo Shen #endif
633225f34eSBo Shen 
643225f34eSBo Shen /* SDRAM */
653225f34eSBo Shen #define CONFIG_NR_DRAM_BANKS		1
663225f34eSBo Shen #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
673225f34eSBo Shen #define CONFIG_SYS_SDRAM_SIZE		0x20000000
683225f34eSBo Shen 
69c5e8885aSBo Shen #ifdef CONFIG_SPL_BUILD
70c5e8885aSBo Shen #define CONFIG_SYS_INIT_SP_ADDR		0x310000
71c5e8885aSBo Shen #else
723225f34eSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \
733225f34eSBo Shen 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
74c5e8885aSBo Shen #endif
753225f34eSBo Shen 
763225f34eSBo Shen /* SerialFlash */
773225f34eSBo Shen #define CONFIG_CMD_SF
783225f34eSBo Shen 
793225f34eSBo Shen #ifdef CONFIG_CMD_SF
803225f34eSBo Shen #define CONFIG_ATMEL_SPI
813225f34eSBo Shen #define CONFIG_SPI_FLASH
823225f34eSBo Shen #define CONFIG_SPI_FLASH_ATMEL
833225f34eSBo Shen #define CONFIG_SF_DEFAULT_SPEED		30000000
843225f34eSBo Shen #endif
853225f34eSBo Shen 
863225f34eSBo Shen /* NAND flash */
873225f34eSBo Shen #define CONFIG_CMD_NAND
883225f34eSBo Shen 
893225f34eSBo Shen #ifdef CONFIG_CMD_NAND
903225f34eSBo Shen #define CONFIG_NAND_ATMEL
913225f34eSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE	1
923225f34eSBo Shen #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
933225f34eSBo Shen /* our ALE is AD21 */
943225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
953225f34eSBo Shen /* our CLE is AD22 */
963225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
973225f34eSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION
983225f34eSBo Shen /* PMECC & PMERRLOC */
993225f34eSBo Shen #define CONFIG_ATMEL_NAND_HWECC
1003225f34eSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC
1013225f34eSBo Shen #define CONFIG_PMECC_CAP		4
1023225f34eSBo Shen #define CONFIG_PMECC_SECTOR_SIZE	512
1033225f34eSBo Shen #define CONFIG_CMD_NAND_TRIMFFS
1043225f34eSBo Shen #endif
1053225f34eSBo Shen 
1063225f34eSBo Shen /* Ethernet Hardware */
1073225f34eSBo Shen #define CONFIG_MACB
1083225f34eSBo Shen #define CONFIG_RMII
1093225f34eSBo Shen #define CONFIG_NET_RETRY_COUNT		20
1103225f34eSBo Shen #define CONFIG_MACB_SEARCH_PHY
111e08d6f3aSBo Shen #define CONFIG_RGMII
112e08d6f3aSBo Shen #define CONFIG_CMD_MII
113e08d6f3aSBo Shen #define CONFIG_PHYLIB
114e08d6f3aSBo Shen #define CONFIG_PHY_MICREL
115e08d6f3aSBo Shen #define CONFIG_PHY_MICREL_KSZ9021
1163225f34eSBo Shen 
1173225f34eSBo Shen /* MMC */
1183225f34eSBo Shen #define CONFIG_CMD_MMC
1193225f34eSBo Shen 
1203225f34eSBo Shen #ifdef CONFIG_CMD_MMC
1213225f34eSBo Shen #define CONFIG_MMC
1223225f34eSBo Shen #define CONFIG_GENERIC_MMC
1233225f34eSBo Shen #define CONFIG_GENERIC_ATMEL_MCI
1243225f34eSBo Shen #define ATMEL_BASE_MMCI			ATMEL_BASE_MCI0
1253225f34eSBo Shen #endif
1263225f34eSBo Shen 
1273225f34eSBo Shen /* USB */
1283225f34eSBo Shen #define CONFIG_CMD_USB
1293225f34eSBo Shen 
1303225f34eSBo Shen #ifdef CONFIG_CMD_USB
1313225f34eSBo Shen #define CONFIG_USB_ATMEL
132dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
1333225f34eSBo Shen #define CONFIG_USB_OHCI_NEW
1343225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT
1353225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
1363225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
1373225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
1383225f34eSBo Shen #define CONFIG_DOS_PARTITION
1393225f34eSBo Shen #define CONFIG_USB_STORAGE
1403225f34eSBo Shen #endif
1413225f34eSBo Shen 
1423668ce3cSBo Shen /* USB device */
1433668ce3cSBo Shen #define CONFIG_USB_GADGET
1443668ce3cSBo Shen #define CONFIG_USB_GADGET_DUALSPEED
1453668ce3cSBo Shen #define CONFIG_USB_GADGET_ATMEL_USBA
1463668ce3cSBo Shen #define CONFIG_USB_ETHER
1473668ce3cSBo Shen #define CONFIG_USB_ETH_RNDIS
1483668ce3cSBo Shen #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
1493668ce3cSBo Shen 
1503225f34eSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
1513225f34eSBo Shen #define CONFIG_CMD_FAT
152a248558aSWu, Josh #define CONFIG_FAT_WRITE
1533225f34eSBo Shen #endif
1543225f34eSBo Shen 
1553225f34eSBo Shen #define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
1563225f34eSBo Shen 
1573225f34eSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH
1583225f34eSBo Shen /* bootstrap + u-boot + env + linux in serial flash */
1593225f34eSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH
1603225f34eSBo Shen #define CONFIG_ENV_OFFSET       0x5000
1613225f34eSBo Shen #define CONFIG_ENV_SIZE         0x3000
1623225f34eSBo Shen #define CONFIG_ENV_SECT_SIZE    0x1000
1633225f34eSBo Shen #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
1643225f34eSBo Shen 				"sf read 0x22000000 0x42000 0x300000; " \
1653225f34eSBo Shen 				"bootm 0x22000000"
1663225f34eSBo Shen #elif CONFIG_SYS_USE_NANDFLASH
1673225f34eSBo Shen /* bootstrap + u-boot + env in nandflash */
1683225f34eSBo Shen #define CONFIG_ENV_IS_IN_NAND
1693225f34eSBo Shen #define CONFIG_ENV_OFFSET		0xc0000
1703225f34eSBo Shen #define CONFIG_ENV_OFFSET_REDUND	0x100000
1713225f34eSBo Shen #define CONFIG_ENV_SIZE			0x20000
1723225f34eSBo Shen #define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
1733225f34eSBo Shen 				"nand read 0x22000000 0x200000 0x600000;" \
1743225f34eSBo Shen 				"bootm 0x22000000 - 0x21000000"
1753225f34eSBo Shen #elif CONFIG_SYS_USE_MMC
1763225f34eSBo Shen /* bootstrap + u-boot + env in sd card */
177a248558aSWu, Josh #define CONFIG_ENV_IS_IN_FAT
178a248558aSWu, Josh #define FAT_ENV_INTERFACE	"mmc"
179a248558aSWu, Josh #define FAT_ENV_FILE		"uboot.env"
180a248558aSWu, Josh #define FAT_ENV_DEVICE_AND_PART	"0"
181a248558aSWu, Josh #define CONFIG_ENV_SIZE		0x4000
1823225f34eSBo Shen #define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
1833225f34eSBo Shen 				"fatload mmc 0:1 0x22000000 uImage; " \
1843225f34eSBo Shen 				"bootm 0x22000000 - 0x21000000"
1853225f34eSBo Shen #else
186a4c79b3aSBo Shen #define CONFIG_ENV_IS_NOWHERE
1873225f34eSBo Shen #endif
1883225f34eSBo Shen 
189c5e8885aSBo Shen /* SPL */
190c5e8885aSBo Shen #define CONFIG_SPL_FRAMEWORK
191c5e8885aSBo Shen #define CONFIG_SPL_TEXT_BASE		0x300000
192c5e8885aSBo Shen #define CONFIG_SPL_MAX_SIZE		0x10000
193c5e8885aSBo Shen #define CONFIG_SPL_BSS_START_ADDR	0x20000000
194c5e8885aSBo Shen #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
195c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_START	0x20080000
196c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
197c5e8885aSBo Shen 
198c5e8885aSBo Shen #define CONFIG_SPL_LIBCOMMON_SUPPORT
199c5e8885aSBo Shen #define CONFIG_SPL_LIBGENERIC_SUPPORT
200c5e8885aSBo Shen #define CONFIG_SPL_GPIO_SUPPORT
201c5e8885aSBo Shen #define CONFIG_SPL_SERIAL_SUPPORT
202c5e8885aSBo Shen 
203c5e8885aSBo Shen #define CONFIG_SPL_BOARD_INIT
2048a45b0baSBo Shen #define CONFIG_SYS_MONITOR_LEN		(512 << 10)
2058a45b0baSBo Shen 
206c5e8885aSBo Shen #ifdef CONFIG_SYS_USE_MMC
207993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/armv7/u-boot-spl.lds
208c5e8885aSBo Shen #define CONFIG_SPL_MMC_SUPPORT
209c5e8885aSBo Shen #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
210c5e8885aSBo Shen #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
211e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
212205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
213c5e8885aSBo Shen #define CONFIG_SPL_FAT_SUPPORT
214c5e8885aSBo Shen #define CONFIG_SPL_LIBDISK_SUPPORT
2158a45b0baSBo Shen 
21627019e4aSBo Shen #elif CONFIG_SYS_USE_NANDFLASH
21727019e4aSBo Shen #define CONFIG_SPL_NAND_SUPPORT
21827019e4aSBo Shen #define CONFIG_SPL_NAND_DRIVERS
21927019e4aSBo Shen #define CONFIG_SPL_NAND_BASE
22027019e4aSBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
22127019e4aSBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE
22227019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
22327019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT	64
22427019e4aSBo Shen #define CONFIG_SYS_NAND_OOBSIZE		64
22527019e4aSBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
22627019e4aSBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
227e166a831SAndreas Bießmann #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
22827019e4aSBo Shen 
2298a45b0baSBo Shen #elif CONFIG_SYS_USE_SERIALFLASH
2308a45b0baSBo Shen #define CONFIG_SPL_SPI_SUPPORT
2318a45b0baSBo Shen #define CONFIG_SPL_SPI_FLASH_SUPPORT
2328a45b0baSBo Shen #define CONFIG_SPL_SPI_LOAD
2338a45b0baSBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
2348a45b0baSBo Shen 
235c5e8885aSBo Shen #endif
236c5e8885aSBo Shen 
2373225f34eSBo Shen #endif
238