13225f34eSBo Shen /* 23225f34eSBo Shen * Configuation settings for the SAMA5D3xEK board. 33225f34eSBo Shen * 43225f34eSBo Shen * Copyright (C) 2012 - 2013 Atmel 53225f34eSBo Shen * 63225f34eSBo Shen * based on at91sam9m10g45ek.h by: 73225f34eSBo Shen * Stelian Pop <stelian@popies.net> 83225f34eSBo Shen * Lead Tech Design <www.leadtechdesign.com> 93225f34eSBo Shen * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 113225f34eSBo Shen */ 123225f34eSBo Shen 133225f34eSBo Shen #ifndef __CONFIG_H 143225f34eSBo Shen #define __CONFIG_H 153225f34eSBo Shen 163225f34eSBo Shen #include <asm/hardware.h> 173225f34eSBo Shen 183225f34eSBo Shen #define CONFIG_SYS_TEXT_BASE 0x26f00000 193225f34eSBo Shen 203225f34eSBo Shen /* ARM asynchronous clock */ 213225f34eSBo Shen #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 223225f34eSBo Shen #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 233225f34eSBo Shen 243225f34eSBo Shen #define CONFIG_AT91FAMILY 253225f34eSBo Shen #define CONFIG_ARCH_CPU_INIT 263225f34eSBo Shen 27c5e8885aSBo Shen #ifndef CONFIG_SPL_BUILD 283225f34eSBo Shen #define CONFIG_SKIP_LOWLEVEL_INIT 29c5e8885aSBo Shen #endif 30c5e8885aSBo Shen 313225f34eSBo Shen #define CONFIG_BOARD_EARLY_INIT_F 323225f34eSBo Shen #define CONFIG_DISPLAY_CPUINFO 333225f34eSBo Shen 343225f34eSBo Shen #define CONFIG_CMD_BOOTZ 353225f34eSBo Shen #define CONFIG_OF_LIBFDT /* Device Tree support */ 363225f34eSBo Shen 37*525049d3SBo Shen #define CONFIG_SYS_GENERIC_BOARD 38*525049d3SBo Shen 393225f34eSBo Shen /* general purpose I/O */ 403225f34eSBo Shen #define CONFIG_AT91_GPIO 413225f34eSBo Shen 423225f34eSBo Shen /* serial console */ 433225f34eSBo Shen #define CONFIG_ATMEL_USART 443225f34eSBo Shen #define CONFIG_USART_BASE ATMEL_BASE_DBGU 453225f34eSBo Shen #define CONFIG_USART_ID ATMEL_ID_DBGU 463225f34eSBo Shen 473225f34eSBo Shen /* 483225f34eSBo Shen * This needs to be defined for the OHCI code to work but it is defined as 493225f34eSBo Shen * ATMEL_ID_UHPHS in the CPU specific header files. 503225f34eSBo Shen */ 513225f34eSBo Shen #define ATMEL_ID_UHP ATMEL_ID_UHPHS 523225f34eSBo Shen 533225f34eSBo Shen /* 543225f34eSBo Shen * Specify the clock enable bit in the PMC_SCER register. 553225f34eSBo Shen */ 563225f34eSBo Shen #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 573225f34eSBo Shen 583225f34eSBo Shen /* LCD */ 593225f34eSBo Shen #define CONFIG_LCD 603225f34eSBo Shen #define LCD_BPP LCD_COLOR16 613225f34eSBo Shen #define LCD_OUTPUT_BPP 24 623225f34eSBo Shen #define CONFIG_LCD_LOGO 633225f34eSBo Shen #define CONFIG_LCD_INFO 643225f34eSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO 653225f34eSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK 663225f34eSBo Shen #define CONFIG_ATMEL_HLCD 673225f34eSBo Shen #define CONFIG_ATMEL_LCD_RGB565 683225f34eSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV 693225f34eSBo Shen 703225f34eSBo Shen /* board specific (not enough SRAM) */ 713225f34eSBo Shen #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 723225f34eSBo Shen 733225f34eSBo Shen #define CONFIG_BOOTDELAY 3 743225f34eSBo Shen 753225f34eSBo Shen /* 763225f34eSBo Shen * BOOTP options 773225f34eSBo Shen */ 783225f34eSBo Shen #define CONFIG_BOOTP_BOOTFILESIZE 793225f34eSBo Shen #define CONFIG_BOOTP_BOOTPATH 803225f34eSBo Shen #define CONFIG_BOOTP_GATEWAY 813225f34eSBo Shen #define CONFIG_BOOTP_HOSTNAME 823225f34eSBo Shen 833225f34eSBo Shen /* No NOR flash */ 843225f34eSBo Shen #define CONFIG_SYS_NO_FLASH 853225f34eSBo Shen 863225f34eSBo Shen /* 873225f34eSBo Shen * Command line configuration. 883225f34eSBo Shen */ 893225f34eSBo Shen #include <config_cmd_default.h> 903225f34eSBo Shen #undef CONFIG_CMD_FPGA 913225f34eSBo Shen #undef CONFIG_CMD_IMI 923225f34eSBo Shen #undef CONFIG_CMD_LOADS 933225f34eSBo Shen #define CONFIG_CMD_PING 943225f34eSBo Shen #define CONFIG_CMD_DHCP 953225f34eSBo Shen 963225f34eSBo Shen /* SDRAM */ 973225f34eSBo Shen #define CONFIG_NR_DRAM_BANKS 1 983225f34eSBo Shen #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 993225f34eSBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x20000000 1003225f34eSBo Shen 101c5e8885aSBo Shen #ifdef CONFIG_SPL_BUILD 102c5e8885aSBo Shen #define CONFIG_SYS_INIT_SP_ADDR 0x310000 103c5e8885aSBo Shen #else 1043225f34eSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 1053225f34eSBo Shen (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 106c5e8885aSBo Shen #endif 1073225f34eSBo Shen 1083225f34eSBo Shen /* SerialFlash */ 1093225f34eSBo Shen #define CONFIG_CMD_SF 1103225f34eSBo Shen 1113225f34eSBo Shen #ifdef CONFIG_CMD_SF 1123225f34eSBo Shen #define CONFIG_ATMEL_SPI 1133225f34eSBo Shen #define CONFIG_SPI_FLASH 1143225f34eSBo Shen #define CONFIG_SPI_FLASH_ATMEL 1153225f34eSBo Shen #define CONFIG_SF_DEFAULT_SPEED 30000000 1163225f34eSBo Shen #endif 1173225f34eSBo Shen 1183225f34eSBo Shen /* NAND flash */ 1193225f34eSBo Shen #define CONFIG_CMD_NAND 1203225f34eSBo Shen 1213225f34eSBo Shen #ifdef CONFIG_CMD_NAND 1223225f34eSBo Shen #define CONFIG_NAND_ATMEL 1233225f34eSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 1243225f34eSBo Shen #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 1253225f34eSBo Shen /* our ALE is AD21 */ 1263225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 1273225f34eSBo Shen /* our CLE is AD22 */ 1283225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 1293225f34eSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 1303225f34eSBo Shen /* PMECC & PMERRLOC */ 1313225f34eSBo Shen #define CONFIG_ATMEL_NAND_HWECC 1323225f34eSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC 1333225f34eSBo Shen #define CONFIG_PMECC_CAP 4 1343225f34eSBo Shen #define CONFIG_PMECC_SECTOR_SIZE 512 1353225f34eSBo Shen #define CONFIG_CMD_NAND_TRIMFFS 1363225f34eSBo Shen #endif 1373225f34eSBo Shen 1383225f34eSBo Shen /* Ethernet Hardware */ 1393225f34eSBo Shen #define CONFIG_MACB 1403225f34eSBo Shen #define CONFIG_RMII 1413225f34eSBo Shen #define CONFIG_NET_RETRY_COUNT 20 1423225f34eSBo Shen #define CONFIG_MACB_SEARCH_PHY 143e08d6f3aSBo Shen #define CONFIG_RGMII 144e08d6f3aSBo Shen #define CONFIG_CMD_MII 145e08d6f3aSBo Shen #define CONFIG_PHYLIB 146e08d6f3aSBo Shen #define CONFIG_PHY_MICREL 147e08d6f3aSBo Shen #define CONFIG_PHY_MICREL_KSZ9021 1483225f34eSBo Shen 1493225f34eSBo Shen /* MMC */ 1503225f34eSBo Shen #define CONFIG_CMD_MMC 1513225f34eSBo Shen 1523225f34eSBo Shen #ifdef CONFIG_CMD_MMC 1533225f34eSBo Shen #define CONFIG_MMC 1543225f34eSBo Shen #define CONFIG_GENERIC_MMC 1553225f34eSBo Shen #define CONFIG_GENERIC_ATMEL_MCI 1563225f34eSBo Shen #define ATMEL_BASE_MMCI ATMEL_BASE_MCI0 1573225f34eSBo Shen #endif 1583225f34eSBo Shen 1593225f34eSBo Shen /* USB */ 1603225f34eSBo Shen #define CONFIG_CMD_USB 1613225f34eSBo Shen 1623225f34eSBo Shen #ifdef CONFIG_CMD_USB 1633225f34eSBo Shen #define CONFIG_USB_ATMEL 164dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 1653225f34eSBo Shen #define CONFIG_USB_OHCI_NEW 1663225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT 1673225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 1683225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" 1693225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 1703225f34eSBo Shen #define CONFIG_DOS_PARTITION 1713225f34eSBo Shen #define CONFIG_USB_STORAGE 1723225f34eSBo Shen #endif 1733225f34eSBo Shen 1743668ce3cSBo Shen /* USB device */ 1753668ce3cSBo Shen #define CONFIG_USB_GADGET 1763668ce3cSBo Shen #define CONFIG_USB_GADGET_DUALSPEED 1773668ce3cSBo Shen #define CONFIG_USB_GADGET_ATMEL_USBA 1783668ce3cSBo Shen #define CONFIG_USB_ETHER 1793668ce3cSBo Shen #define CONFIG_USB_ETH_RNDIS 1803668ce3cSBo Shen #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" 1813668ce3cSBo Shen 1823225f34eSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) 1833225f34eSBo Shen #define CONFIG_CMD_FAT 1843225f34eSBo Shen #endif 1853225f34eSBo Shen 1863225f34eSBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 1873225f34eSBo Shen 1883225f34eSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH 1893225f34eSBo Shen /* bootstrap + u-boot + env + linux in serial flash */ 1903225f34eSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH 1913225f34eSBo Shen #define CONFIG_ENV_OFFSET 0x5000 1923225f34eSBo Shen #define CONFIG_ENV_SIZE 0x3000 1933225f34eSBo Shen #define CONFIG_ENV_SECT_SIZE 0x1000 1943225f34eSBo Shen #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 1953225f34eSBo Shen "sf read 0x22000000 0x42000 0x300000; " \ 1963225f34eSBo Shen "bootm 0x22000000" 1973225f34eSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 1983225f34eSBo Shen /* bootstrap + u-boot + env in nandflash */ 1993225f34eSBo Shen #define CONFIG_ENV_IS_IN_NAND 2003225f34eSBo Shen #define CONFIG_ENV_OFFSET 0xc0000 2013225f34eSBo Shen #define CONFIG_ENV_OFFSET_REDUND 0x100000 2023225f34eSBo Shen #define CONFIG_ENV_SIZE 0x20000 2033225f34eSBo Shen #define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ 2043225f34eSBo Shen "nand read 0x22000000 0x200000 0x600000;" \ 2053225f34eSBo Shen "bootm 0x22000000 - 0x21000000" 2063225f34eSBo Shen #elif CONFIG_SYS_USE_MMC 2073225f34eSBo Shen /* bootstrap + u-boot + env in sd card */ 2083225f34eSBo Shen #define CONFIG_ENV_IS_IN_MMC 2093225f34eSBo Shen #define CONFIG_ENV_OFFSET 0x2000 2103225f34eSBo Shen #define CONFIG_ENV_SIZE 0x1000 2113225f34eSBo Shen #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ 2123225f34eSBo Shen "fatload mmc 0:1 0x22000000 uImage; " \ 2133225f34eSBo Shen "bootm 0x22000000 - 0x21000000" 2143225f34eSBo Shen #define CONFIG_SYS_MMC_ENV_DEV 0 2153225f34eSBo Shen #else 216a4c79b3aSBo Shen #define CONFIG_ENV_IS_NOWHERE 2173225f34eSBo Shen #endif 2183225f34eSBo Shen 2193225f34eSBo Shen #ifdef CONFIG_SYS_USE_MMC 2203225f34eSBo Shen #define CONFIG_BOOTARGS \ 2213225f34eSBo Shen "console=ttyS0,115200 earlyprintk " \ 2223225f34eSBo Shen "root=/dev/mmcblk0p2 rw rootwait" 2233225f34eSBo Shen #else 2243225f34eSBo Shen #define CONFIG_BOOTARGS \ 2253225f34eSBo Shen "console=ttyS0,115200 earlyprintk " \ 2263225f34eSBo Shen "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 2273225f34eSBo Shen "256K(env),256k(evn_redundent),256k(spare)," \ 2283225f34eSBo Shen "512k(dtb),6M(kernel)ro,-(rootfs) " \ 2293225f34eSBo Shen "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" 2303225f34eSBo Shen #endif 2313225f34eSBo Shen 2323225f34eSBo Shen #define CONFIG_BAUDRATE 115200 2333225f34eSBo Shen 2343225f34eSBo Shen #define CONFIG_SYS_PROMPT "U-Boot> " 2353225f34eSBo Shen #define CONFIG_SYS_CBSIZE 256 2363225f34eSBo Shen #define CONFIG_SYS_MAXARGS 16 2373225f34eSBo Shen #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 2383225f34eSBo Shen sizeof(CONFIG_SYS_PROMPT) + 16) 2393225f34eSBo Shen #define CONFIG_SYS_LONGHELP 2403225f34eSBo Shen #define CONFIG_CMDLINE_EDITING 2413225f34eSBo Shen #define CONFIG_AUTO_COMPLETE 2423225f34eSBo Shen #define CONFIG_SYS_HUSH_PARSER 2433225f34eSBo Shen 2443225f34eSBo Shen /* Size of malloc() pool */ 2453225f34eSBo Shen #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 2463225f34eSBo Shen 247c5e8885aSBo Shen /* SPL */ 248c5e8885aSBo Shen #define CONFIG_SPL 249c5e8885aSBo Shen #define CONFIG_SPL_FRAMEWORK 250c5e8885aSBo Shen #define CONFIG_SPL_TEXT_BASE 0x300000 251c5e8885aSBo Shen #define CONFIG_SPL_MAX_SIZE 0x10000 252c5e8885aSBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 253c5e8885aSBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 254c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 255c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 256c5e8885aSBo Shen 257c5e8885aSBo Shen #define CONFIG_SPL_LIBCOMMON_SUPPORT 258c5e8885aSBo Shen #define CONFIG_SPL_LIBGENERIC_SUPPORT 259c5e8885aSBo Shen #define CONFIG_SPL_GPIO_SUPPORT 260c5e8885aSBo Shen #define CONFIG_SPL_SERIAL_SUPPORT 261c5e8885aSBo Shen 262c5e8885aSBo Shen #define CONFIG_SPL_BOARD_INIT 2638a45b0baSBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 2648a45b0baSBo Shen 265c5e8885aSBo Shen #ifdef CONFIG_SYS_USE_MMC 266c5e8885aSBo Shen #define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds 267c5e8885aSBo Shen #define CONFIG_SPL_MMC_SUPPORT 268c5e8885aSBo Shen #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 269c5e8885aSBo Shen #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 270c5e8885aSBo Shen #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 271c5e8885aSBo Shen #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 272c5e8885aSBo Shen #define CONFIG_SPL_FAT_SUPPORT 273c5e8885aSBo Shen #define CONFIG_SPL_LIBDISK_SUPPORT 2748a45b0baSBo Shen 27527019e4aSBo Shen #elif CONFIG_SYS_USE_NANDFLASH 27627019e4aSBo Shen #define CONFIG_SPL_NAND_SUPPORT 27727019e4aSBo Shen #define CONFIG_SPL_NAND_DRIVERS 27827019e4aSBo Shen #define CONFIG_SPL_NAND_BASE 27927019e4aSBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 28027019e4aSBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 28127019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 28227019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 28327019e4aSBo Shen #define CONFIG_SYS_NAND_OOBSIZE 64 28427019e4aSBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 28527019e4aSBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 28627019e4aSBo Shen 2878a45b0baSBo Shen #elif CONFIG_SYS_USE_SERIALFLASH 2888a45b0baSBo Shen #define CONFIG_SPL_SPI_SUPPORT 2898a45b0baSBo Shen #define CONFIG_SPL_SPI_FLASH_SUPPORT 2908a45b0baSBo Shen #define CONFIG_SPL_SPI_LOAD 2918a45b0baSBo Shen #define CONFIG_SPL_SPI_BUS 0 2928a45b0baSBo Shen #define CONFIG_SPL_SPI_CS 0 2938a45b0baSBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 2948a45b0baSBo Shen 295c5e8885aSBo Shen #endif 296c5e8885aSBo Shen 2973225f34eSBo Shen #endif 298