xref: /rk3399_rockchip-uboot/include/configs/sama5d3xek.h (revision 372ca03fcd3cc777677d683336e9965c02fc42f2)
13225f34eSBo Shen /*
23225f34eSBo Shen  * Configuation settings for the SAMA5D3xEK board.
33225f34eSBo Shen  *
43225f34eSBo Shen  * Copyright (C) 2012 - 2013 Atmel
53225f34eSBo Shen  *
63225f34eSBo Shen  * based on at91sam9m10g45ek.h by:
73225f34eSBo Shen  * Stelian Pop <stelian@popies.net>
83225f34eSBo Shen  * Lead Tech Design <www.leadtechdesign.com>
93225f34eSBo Shen  *
101a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
113225f34eSBo Shen  */
123225f34eSBo Shen 
133225f34eSBo Shen #ifndef __CONFIG_H
143225f34eSBo Shen #define __CONFIG_H
153225f34eSBo Shen 
16b2d387bcSWu, Josh /*
17b2d387bcSWu, Josh  * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
18b2d387bcSWu, Josh  * before the common header.
19b2d387bcSWu, Josh  */
20b2d387bcSWu, Josh #include "at91-sama5_common.h"
213225f34eSBo Shen 
223225f34eSBo Shen /* serial console */
233225f34eSBo Shen #define CONFIG_ATMEL_USART
243225f34eSBo Shen #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
253225f34eSBo Shen #define	CONFIG_USART_ID			ATMEL_ID_DBGU
263225f34eSBo Shen 
273225f34eSBo Shen /*
283225f34eSBo Shen  * This needs to be defined for the OHCI code to work but it is defined as
293225f34eSBo Shen  * ATMEL_ID_UHPHS in the CPU specific header files.
303225f34eSBo Shen  */
313225f34eSBo Shen #define ATMEL_ID_UHP			ATMEL_ID_UHPHS
323225f34eSBo Shen 
333225f34eSBo Shen /*
343225f34eSBo Shen  * Specify the clock enable bit in the PMC_SCER register.
353225f34eSBo Shen  */
363225f34eSBo Shen #define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
373225f34eSBo Shen 
383225f34eSBo Shen /* LCD */
393225f34eSBo Shen #define CONFIG_LCD
403225f34eSBo Shen #define LCD_BPP				LCD_COLOR16
413225f34eSBo Shen #define LCD_OUTPUT_BPP                  24
423225f34eSBo Shen #define CONFIG_LCD_LOGO
433225f34eSBo Shen #define CONFIG_LCD_INFO
443225f34eSBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO
453225f34eSBo Shen #define CONFIG_SYS_WHITE_ON_BLACK
463225f34eSBo Shen #define CONFIG_ATMEL_HLCD
473225f34eSBo Shen #define CONFIG_ATMEL_LCD_RGB565
483225f34eSBo Shen #define CONFIG_SYS_CONSOLE_IS_IN_ENV
493225f34eSBo Shen 
503225f34eSBo Shen /* board specific (not enough SRAM) */
513225f34eSBo Shen #define CONFIG_SAMA5D3_LCD_BASE		0x23E00000
523225f34eSBo Shen 
53d6b79434SBo Shen /* NOR flash */
54b2d387bcSWu, Josh #ifndef CONFIG_SYS_NO_FLASH
55d6b79434SBo Shen #define CONFIG_FLASH_CFI_DRIVER
56d6b79434SBo Shen #define CONFIG_SYS_FLASH_CFI
57d6b79434SBo Shen #define CONFIG_SYS_FLASH_PROTECTION
58d6b79434SBo Shen #define CONFIG_SYS_FLASH_BASE		0x10000000
59d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_SECT	131
60d6b79434SBo Shen #define CONFIG_SYS_MAX_FLASH_BANKS	1
61d6b79434SBo Shen #endif
623225f34eSBo Shen 
633225f34eSBo Shen /* SDRAM */
643225f34eSBo Shen #define CONFIG_NR_DRAM_BANKS		1
653225f34eSBo Shen #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
663225f34eSBo Shen #define CONFIG_SYS_SDRAM_SIZE		0x20000000
673225f34eSBo Shen 
68c5e8885aSBo Shen #ifdef CONFIG_SPL_BUILD
69c5e8885aSBo Shen #define CONFIG_SYS_INIT_SP_ADDR		0x310000
70c5e8885aSBo Shen #else
713225f34eSBo Shen #define CONFIG_SYS_INIT_SP_ADDR \
723225f34eSBo Shen 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
73c5e8885aSBo Shen #endif
743225f34eSBo Shen 
753225f34eSBo Shen /* SerialFlash */
763225f34eSBo Shen #define CONFIG_CMD_SF
773225f34eSBo Shen 
783225f34eSBo Shen #ifdef CONFIG_CMD_SF
793225f34eSBo Shen #define CONFIG_ATMEL_SPI
803225f34eSBo Shen #define CONFIG_SPI_FLASH_ATMEL
813225f34eSBo Shen #define CONFIG_SF_DEFAULT_SPEED		30000000
823225f34eSBo Shen #endif
833225f34eSBo Shen 
843225f34eSBo Shen /* NAND flash */
853225f34eSBo Shen #define CONFIG_CMD_NAND
863225f34eSBo Shen 
873225f34eSBo Shen #ifdef CONFIG_CMD_NAND
883225f34eSBo Shen #define CONFIG_NAND_ATMEL
893225f34eSBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE	1
903225f34eSBo Shen #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
913225f34eSBo Shen /* our ALE is AD21 */
923225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
933225f34eSBo Shen /* our CLE is AD22 */
943225f34eSBo Shen #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
953225f34eSBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION
963225f34eSBo Shen /* PMECC & PMERRLOC */
973225f34eSBo Shen #define CONFIG_ATMEL_NAND_HWECC
983225f34eSBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC
993225f34eSBo Shen #define CONFIG_PMECC_CAP		4
1003225f34eSBo Shen #define CONFIG_PMECC_SECTOR_SIZE	512
1013225f34eSBo Shen #define CONFIG_CMD_NAND_TRIMFFS
1023225f34eSBo Shen #endif
1033225f34eSBo Shen 
1043225f34eSBo Shen /* Ethernet Hardware */
1053225f34eSBo Shen #define CONFIG_MACB
1063225f34eSBo Shen #define CONFIG_RMII
1073225f34eSBo Shen #define CONFIG_NET_RETRY_COUNT		20
1083225f34eSBo Shen #define CONFIG_MACB_SEARCH_PHY
109e08d6f3aSBo Shen #define CONFIG_RGMII
110e08d6f3aSBo Shen #define CONFIG_CMD_MII
111e08d6f3aSBo Shen #define CONFIG_PHYLIB
112e08d6f3aSBo Shen #define CONFIG_PHY_MICREL
113e08d6f3aSBo Shen #define CONFIG_PHY_MICREL_KSZ9021
1143225f34eSBo Shen 
1153225f34eSBo Shen /* MMC */
1163225f34eSBo Shen #define CONFIG_CMD_MMC
1173225f34eSBo Shen 
1183225f34eSBo Shen #ifdef CONFIG_CMD_MMC
1193225f34eSBo Shen #define CONFIG_MMC
1203225f34eSBo Shen #define CONFIG_GENERIC_MMC
1213225f34eSBo Shen #define CONFIG_GENERIC_ATMEL_MCI
1223225f34eSBo Shen #define ATMEL_BASE_MMCI			ATMEL_BASE_MCI0
1233225f34eSBo Shen #endif
1243225f34eSBo Shen 
1253225f34eSBo Shen /* USB */
1263225f34eSBo Shen #define CONFIG_CMD_USB
1273225f34eSBo Shen 
1283225f34eSBo Shen #ifdef CONFIG_CMD_USB
1293225f34eSBo Shen #define CONFIG_USB_ATMEL
130dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
1313225f34eSBo Shen #define CONFIG_USB_OHCI_NEW
1323225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT
1333225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
1343225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
1353225f34eSBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
1363225f34eSBo Shen #define CONFIG_DOS_PARTITION
1373225f34eSBo Shen #define CONFIG_USB_STORAGE
1383225f34eSBo Shen #endif
1393225f34eSBo Shen 
1403668ce3cSBo Shen /* USB device */
1413668ce3cSBo Shen #define CONFIG_USB_GADGET
1423668ce3cSBo Shen #define CONFIG_USB_GADGET_DUALSPEED
1433668ce3cSBo Shen #define CONFIG_USB_GADGET_ATMEL_USBA
1443668ce3cSBo Shen #define CONFIG_USB_ETHER
1453668ce3cSBo Shen #define CONFIG_USB_ETH_RNDIS
1463668ce3cSBo Shen #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
1473668ce3cSBo Shen 
1483225f34eSBo Shen #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
1493225f34eSBo Shen #define CONFIG_CMD_FAT
150a248558aSWu, Josh #define CONFIG_FAT_WRITE
1513225f34eSBo Shen #endif
1523225f34eSBo Shen 
1533225f34eSBo Shen #define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
1543225f34eSBo Shen 
1553225f34eSBo Shen #ifdef CONFIG_SYS_USE_SERIALFLASH
1563225f34eSBo Shen /* bootstrap + u-boot + env + linux in serial flash */
1573225f34eSBo Shen #define CONFIG_ENV_IS_IN_SPI_FLASH
1583225f34eSBo Shen #define CONFIG_ENV_OFFSET       0x5000
1593225f34eSBo Shen #define CONFIG_ENV_SIZE         0x3000
1603225f34eSBo Shen #define CONFIG_ENV_SECT_SIZE    0x1000
1613225f34eSBo Shen #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
1623225f34eSBo Shen 				"sf read 0x22000000 0x42000 0x300000; " \
1633225f34eSBo Shen 				"bootm 0x22000000"
1643225f34eSBo Shen #elif CONFIG_SYS_USE_NANDFLASH
1653225f34eSBo Shen /* bootstrap + u-boot + env in nandflash */
1663225f34eSBo Shen #define CONFIG_ENV_IS_IN_NAND
1673225f34eSBo Shen #define CONFIG_ENV_OFFSET		0xc0000
1683225f34eSBo Shen #define CONFIG_ENV_OFFSET_REDUND	0x100000
1693225f34eSBo Shen #define CONFIG_ENV_SIZE			0x20000
1703225f34eSBo Shen #define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
1713225f34eSBo Shen 				"nand read 0x22000000 0x200000 0x600000;" \
1723225f34eSBo Shen 				"bootm 0x22000000 - 0x21000000"
1733225f34eSBo Shen #elif CONFIG_SYS_USE_MMC
174*372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */
1753225f34eSBo Shen #else
176a4c79b3aSBo Shen #define CONFIG_ENV_IS_NOWHERE
1773225f34eSBo Shen #endif
1783225f34eSBo Shen 
179c5e8885aSBo Shen /* SPL */
180c5e8885aSBo Shen #define CONFIG_SPL_FRAMEWORK
181c5e8885aSBo Shen #define CONFIG_SPL_TEXT_BASE		0x300000
182c5e8885aSBo Shen #define CONFIG_SPL_MAX_SIZE		0x10000
183c5e8885aSBo Shen #define CONFIG_SPL_BSS_START_ADDR	0x20000000
184c5e8885aSBo Shen #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
185c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_START	0x20080000
186c5e8885aSBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
187c5e8885aSBo Shen 
188c5e8885aSBo Shen #define CONFIG_SPL_LIBCOMMON_SUPPORT
189c5e8885aSBo Shen #define CONFIG_SPL_LIBGENERIC_SUPPORT
190c5e8885aSBo Shen #define CONFIG_SPL_GPIO_SUPPORT
191c5e8885aSBo Shen #define CONFIG_SPL_SERIAL_SUPPORT
192c5e8885aSBo Shen 
193c5e8885aSBo Shen #define CONFIG_SPL_BOARD_INIT
1948a45b0baSBo Shen #define CONFIG_SYS_MONITOR_LEN		(512 << 10)
1958a45b0baSBo Shen 
196c5e8885aSBo Shen #ifdef CONFIG_SYS_USE_MMC
197993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/armv7/u-boot-spl.lds
198c5e8885aSBo Shen #define CONFIG_SPL_MMC_SUPPORT
199c5e8885aSBo Shen #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
200c5e8885aSBo Shen #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
201e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
202205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
203c5e8885aSBo Shen #define CONFIG_SPL_FAT_SUPPORT
204c5e8885aSBo Shen #define CONFIG_SPL_LIBDISK_SUPPORT
2058a45b0baSBo Shen 
20627019e4aSBo Shen #elif CONFIG_SYS_USE_NANDFLASH
20727019e4aSBo Shen #define CONFIG_SPL_NAND_SUPPORT
20827019e4aSBo Shen #define CONFIG_SPL_NAND_DRIVERS
20927019e4aSBo Shen #define CONFIG_SPL_NAND_BASE
21027019e4aSBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
21127019e4aSBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE
21227019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
21327019e4aSBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT	64
21427019e4aSBo Shen #define CONFIG_SYS_NAND_OOBSIZE		64
21527019e4aSBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
21627019e4aSBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
217e166a831SAndreas Bießmann #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
21827019e4aSBo Shen 
2198a45b0baSBo Shen #elif CONFIG_SYS_USE_SERIALFLASH
2208a45b0baSBo Shen #define CONFIG_SPL_SPI_SUPPORT
2218a45b0baSBo Shen #define CONFIG_SPL_SPI_FLASH_SUPPORT
2228a45b0baSBo Shen #define CONFIG_SPL_SPI_LOAD
2238a45b0baSBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
2248a45b0baSBo Shen 
225c5e8885aSBo Shen #endif
226c5e8885aSBo Shen 
2273225f34eSBo Shen #endif
228