1 /* 2 * Configuration settings for the SAMA5D3 Xplained board. 3 * 4 * Copyright (C) 2014 Atmel Corporation 5 * Bo Shen <voice.shen@atmel.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "at91-sama5_common.h" 14 15 /* 16 * This needs to be defined for the OHCI code to work but it is defined as 17 * ATMEL_ID_UHPHS in the CPU specific header files. 18 */ 19 #define ATMEL_ID_UHP ATMEL_ID_UHPHS 20 21 /* 22 * Specify the clock enable bit in the PMC_SCER register. 23 */ 24 #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 25 26 /* SDRAM */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 29 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 30 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_SYS_INIT_SP_ADDR 0x318000 33 #else 34 #define CONFIG_SYS_INIT_SP_ADDR \ 35 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 36 #endif 37 38 /* NAND flash */ 39 #ifdef CONFIG_CMD_NAND 40 #define CONFIG_SYS_MAX_NAND_DEVICE 1 41 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 42 /* our ALE is AD21 */ 43 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 44 /* our CLE is AD22 */ 45 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 46 #define CONFIG_SYS_NAND_ONFI_DETECTION 47 #endif 48 /* PMECC & PMERRLOC */ 49 #define CONFIG_ATMEL_NAND_HWECC 50 #define CONFIG_ATMEL_NAND_HW_PMECC 51 #define CONFIG_PMECC_CAP 4 52 #define CONFIG_PMECC_SECTOR_SIZE 512 53 54 /* USB */ 55 56 #ifdef CONFIG_CMD_USB 57 #define CONFIG_USB_ATMEL 58 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 59 #define CONFIG_USB_OHCI_NEW 60 #define CONFIG_SYS_USB_OHCI_CPU_INIT 61 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 62 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" 63 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 64 #endif 65 66 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 67 68 #if CONFIG_SYS_USE_NANDFLASH 69 /* override the bootcmd, bootargs and other configuration for nandflash env */ 70 #elif CONFIG_SYS_USE_MMC 71 /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 72 #endif 73 74 /* SPL */ 75 #define CONFIG_SPL_FRAMEWORK 76 #define CONFIG_SPL_TEXT_BASE 0x300000 77 #define CONFIG_SPL_MAX_SIZE 0x18000 78 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 79 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 80 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 81 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 82 83 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 84 85 #ifdef CONFIG_SYS_USE_MMC 86 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 87 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 88 89 #elif CONFIG_SYS_USE_NANDFLASH 90 #define CONFIG_SPL_NAND_DRIVERS 91 #define CONFIG_SPL_NAND_BASE 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 93 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 94 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 95 #define CONFIG_SYS_NAND_PAGE_COUNT 64 96 #define CONFIG_SYS_NAND_OOBSIZE 64 97 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 98 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 99 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 100 101 #endif 102 103 #endif 104