xref: /rk3399_rockchip-uboot/include/configs/sama5d3_xplained.h (revision 8f1a80e99e4a838d1540cdb1d59ccc7785fe4618)
17ca6f363SBo Shen /*
27ca6f363SBo Shen  * Configuration settings for the SAMA5D3 Xplained board.
37ca6f363SBo Shen  *
47ca6f363SBo Shen  * Copyright (C) 2014 Atmel Corporation
57ca6f363SBo Shen  *		      Bo Shen <voice.shen@atmel.com>
67ca6f363SBo Shen  *
77ca6f363SBo Shen  * SPDX-License-Identifier:	GPL-2.0+
87ca6f363SBo Shen  */
97ca6f363SBo Shen 
107ca6f363SBo Shen #ifndef __CONFIG_H
117ca6f363SBo Shen #define __CONFIG_H
127ca6f363SBo Shen 
13b2d387bcSWu, Josh #include "at91-sama5_common.h"
147ca6f363SBo Shen 
157ca6f363SBo Shen /*
167ca6f363SBo Shen  * This needs to be defined for the OHCI code to work but it is defined as
177ca6f363SBo Shen  * ATMEL_ID_UHPHS in the CPU specific header files.
187ca6f363SBo Shen  */
197ca6f363SBo Shen #define ATMEL_ID_UHP			ATMEL_ID_UHPHS
207ca6f363SBo Shen 
217ca6f363SBo Shen /*
227ca6f363SBo Shen  * Specify the clock enable bit in the PMC_SCER register.
237ca6f363SBo Shen  */
247ca6f363SBo Shen #define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
257ca6f363SBo Shen 
267ca6f363SBo Shen /* SDRAM */
277ca6f363SBo Shen #define CONFIG_NR_DRAM_BANKS		1
287ca6f363SBo Shen #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
297ca6f363SBo Shen #define CONFIG_SYS_SDRAM_SIZE		0x10000000
307ca6f363SBo Shen 
31cd23aac4SBo Shen #ifdef CONFIG_SPL_BUILD
321878804aSWenyou Yang #define CONFIG_SYS_INIT_SP_ADDR		0x318000
33cd23aac4SBo Shen #else
347ca6f363SBo Shen #define CONFIG_SYS_INIT_SP_ADDR \
351878804aSWenyou Yang 	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
36cd23aac4SBo Shen #endif
377ca6f363SBo Shen 
387ca6f363SBo Shen /* NAND flash */
397ca6f363SBo Shen #ifdef CONFIG_CMD_NAND
407ca6f363SBo Shen #define CONFIG_NAND_ATMEL
417ca6f363SBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE	1
427ca6f363SBo Shen #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
437ca6f363SBo Shen /* our ALE is AD21 */
447ca6f363SBo Shen #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
457ca6f363SBo Shen /* our CLE is AD22 */
467ca6f363SBo Shen #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
477ca6f363SBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION
48*8f1a80e9STom Rini 
49*8f1a80e9STom Rini #define CONFIG_MTD_DEVICE
50*8f1a80e9STom Rini #define CONFIG_MTD_PARTITIONS
51*8f1a80e9STom Rini #endif
527ca6f363SBo Shen /* PMECC & PMERRLOC */
537ca6f363SBo Shen #define CONFIG_ATMEL_NAND_HWECC
547ca6f363SBo Shen #define CONFIG_ATMEL_NAND_HW_PMECC
557ca6f363SBo Shen #define CONFIG_PMECC_CAP		4
567ca6f363SBo Shen #define CONFIG_PMECC_SECTOR_SIZE	512
577ca6f363SBo Shen 
587ca6f363SBo Shen /* USB */
597ca6f363SBo Shen 
607ca6f363SBo Shen #ifdef CONFIG_CMD_USB
617ca6f363SBo Shen #define CONFIG_USB_ATMEL
627ca6f363SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
637ca6f363SBo Shen #define CONFIG_USB_OHCI_NEW
647ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT
657ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
667ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
677ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
687ca6f363SBo Shen #endif
697ca6f363SBo Shen 
707ca6f363SBo Shen #define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
717ca6f363SBo Shen 
727ca6f363SBo Shen #if CONFIG_SYS_USE_NANDFLASH
73dc018fefSWu, Josh /* override the bootcmd, bootargs and other configuration for nandflash env */
747ca6f363SBo Shen #elif CONFIG_SYS_USE_MMC
75372ca03fSWu, Josh /* override the bootcmd, bootargs and other configuration for sd/mmc env */
767ca6f363SBo Shen #endif
777ca6f363SBo Shen 
78cd23aac4SBo Shen /* SPL */
79cd23aac4SBo Shen #define CONFIG_SPL_FRAMEWORK
80cd23aac4SBo Shen #define CONFIG_SPL_TEXT_BASE		0x300000
811878804aSWenyou Yang #define CONFIG_SPL_MAX_SIZE		0x18000
82cd23aac4SBo Shen #define CONFIG_SPL_BSS_START_ADDR	0x20000000
83cd23aac4SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
84cd23aac4SBo Shen #define CONFIG_SYS_SPL_MALLOC_START	0x20080000
85cd23aac4SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
86cd23aac4SBo Shen 
87cd23aac4SBo Shen #define CONFIG_SYS_MONITOR_LEN		(512 << 10)
88cd23aac4SBo Shen 
89cd23aac4SBo Shen #ifdef CONFIG_SYS_USE_MMC
90993ea97eSBo Shen #define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/armv7/u-boot-spl.lds
91e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
92205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
93cd23aac4SBo Shen 
94cd23aac4SBo Shen #elif CONFIG_SYS_USE_NANDFLASH
95cd23aac4SBo Shen #define CONFIG_SPL_NAND_DRIVERS
96cd23aac4SBo Shen #define CONFIG_SPL_NAND_BASE
97cd23aac4SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
98cd23aac4SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE
99cd23aac4SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
100cd23aac4SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT	64
101cd23aac4SBo Shen #define CONFIG_SYS_NAND_OOBSIZE		64
102cd23aac4SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
103cd23aac4SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
10405a4d544SWu, Josh #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
105cd23aac4SBo Shen 
106cd23aac4SBo Shen #endif
107cd23aac4SBo Shen 
1087ca6f363SBo Shen #endif
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