1*2cce6f54SAdam Ford /* SPDX-License-Identifier: GPL-2.0+ */ 2*2cce6f54SAdam Ford /* 3*2cce6f54SAdam Ford * Configuration file for the SAMA5D2 PTC EK Board. 4*2cce6f54SAdam Ford * 5*2cce6f54SAdam Ford * Copyright (C) 2017 Microchip Technology Inc. 6*2cce6f54SAdam Ford * Wenyou Yang <wenyou.yang@microchip.com> 7*2cce6f54SAdam Ford * Ludovic Desroches <ludovic.desroches@microchip.com> 8*2cce6f54SAdam Ford */ 9*2cce6f54SAdam Ford 10*2cce6f54SAdam Ford #ifndef __CONFIG_H 11*2cce6f54SAdam Ford #define __CONFIG_H 12*2cce6f54SAdam Ford 13*2cce6f54SAdam Ford #include "at91-sama5_common.h" 14*2cce6f54SAdam Ford 15*2cce6f54SAdam Ford #undef CONFIG_SYS_AT91_MAIN_CLOCK 16*2cce6f54SAdam Ford #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ 17*2cce6f54SAdam Ford 18*2cce6f54SAdam Ford #define CONFIG_MISC_INIT_R 19*2cce6f54SAdam Ford 20*2cce6f54SAdam Ford /* SDRAM */ 21*2cce6f54SAdam Ford #define CONFIG_NR_DRAM_BANKS 1 22*2cce6f54SAdam Ford #define CONFIG_SYS_SDRAM_BASE 0x20000000 23*2cce6f54SAdam Ford #define CONFIG_SYS_SDRAM_SIZE 0x20000000 24*2cce6f54SAdam Ford 25*2cce6f54SAdam Ford #define CONFIG_SYS_INIT_SP_ADDR \ 26*2cce6f54SAdam Ford (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 27*2cce6f54SAdam Ford 28*2cce6f54SAdam Ford #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 29*2cce6f54SAdam Ford 30*2cce6f54SAdam Ford /* NAND Flash */ 31*2cce6f54SAdam Ford #ifdef CONFIG_CMD_NAND 32*2cce6f54SAdam Ford #define CONFIG_SYS_MAX_NAND_DEVICE 1 33*2cce6f54SAdam Ford #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 34*2cce6f54SAdam Ford /* our ALE is AD21 */ 35*2cce6f54SAdam Ford #define CONFIG_SYS_NAND_MASK_ALE BIT(21) 36*2cce6f54SAdam Ford /* our CLE is AD22 */ 37*2cce6f54SAdam Ford #define CONFIG_SYS_NAND_MASK_CLE BIT(22) 38*2cce6f54SAdam Ford #define CONFIG_SYS_NAND_ONFI_DETECTION 39*2cce6f54SAdam Ford #endif 40*2cce6f54SAdam Ford 41*2cce6f54SAdam Ford #endif /* __CONFIG_H */ 42