1*e525d34bSNobuhiro Iwamatsu /* 2*e525d34bSNobuhiro Iwamatsu * include/configs/salvator-x.h 3*e525d34bSNobuhiro Iwamatsu * This file is Salvator-X board configuration. 4*e525d34bSNobuhiro Iwamatsu * 5*e525d34bSNobuhiro Iwamatsu * Copyright (C) 2015 Renesas Electronics Corporation 6*e525d34bSNobuhiro Iwamatsu * 7*e525d34bSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 8*e525d34bSNobuhiro Iwamatsu */ 9*e525d34bSNobuhiro Iwamatsu 10*e525d34bSNobuhiro Iwamatsu #ifndef __SALVATOR_X_H 11*e525d34bSNobuhiro Iwamatsu #define __SALVATOR_X_H 12*e525d34bSNobuhiro Iwamatsu 13*e525d34bSNobuhiro Iwamatsu #undef DEBUG 14*e525d34bSNobuhiro Iwamatsu 15*e525d34bSNobuhiro Iwamatsu #define CONFIG_RCAR_BOARD_STRING "Salvator-X" 16*e525d34bSNobuhiro Iwamatsu 17*e525d34bSNobuhiro Iwamatsu #include "rcar-gen3-common.h" 18*e525d34bSNobuhiro Iwamatsu 19*e525d34bSNobuhiro Iwamatsu /* SCIF */ 20*e525d34bSNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 21*e525d34bSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF2 22*e525d34bSNobuhiro Iwamatsu #define CONFIG_CONS_INDEX 2 23*e525d34bSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 24*e525d34bSNobuhiro Iwamatsu 25*e525d34bSNobuhiro Iwamatsu /* [A] Hyper Flash */ 26*e525d34bSNobuhiro Iwamatsu /* use to RPC(SPI Multi I/O Bus Controller) */ 27*e525d34bSNobuhiro Iwamatsu #define CONFIG_SYS_NO_FLASH 28*e525d34bSNobuhiro Iwamatsu #define CONFIG_ENV_IS_NOWHERE 29*e525d34bSNobuhiro Iwamatsu 30*e525d34bSNobuhiro Iwamatsu /* Board Clock */ 31*e525d34bSNobuhiro Iwamatsu /* XTAL_CLK : 33.33MHz */ 32*e525d34bSNobuhiro Iwamatsu #define RCAR_XTAL_CLK 33333333u 33*e525d34bSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 34*e525d34bSNobuhiro Iwamatsu /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 35*e525d34bSNobuhiro Iwamatsu /* CPclk 16.66MHz, S3D2 133.33MHz */ 36*e525d34bSNobuhiro Iwamatsu #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 37*e525d34bSNobuhiro Iwamatsu #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 38*e525d34bSNobuhiro Iwamatsu #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 39*e525d34bSNobuhiro Iwamatsu 40*e525d34bSNobuhiro Iwamatsu /* Generic Timer Definitions (use in assembler source) */ 41*e525d34bSNobuhiro Iwamatsu #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 42*e525d34bSNobuhiro Iwamatsu 43*e525d34bSNobuhiro Iwamatsu /* Generic Interrupt Controller Definitions */ 44*e525d34bSNobuhiro Iwamatsu #define CONFIG_GICV2 45*e525d34bSNobuhiro Iwamatsu #define GICD_BASE 0xF1010000 46*e525d34bSNobuhiro Iwamatsu #define GICC_BASE 0xF1020000 47*e525d34bSNobuhiro Iwamatsu 48*e525d34bSNobuhiro Iwamatsu /* Module stop status bits */ 49*e525d34bSNobuhiro Iwamatsu /* MFIS, SCIF1 */ 50*e525d34bSNobuhiro Iwamatsu #define CONFIG_SMSTP2_ENA 0x00002040 51*e525d34bSNobuhiro Iwamatsu /* INTC-AP, IRQC */ 52*e525d34bSNobuhiro Iwamatsu #define CONFIG_SMSTP4_ENA 0x00000180 53*e525d34bSNobuhiro Iwamatsu 54*e525d34bSNobuhiro Iwamatsu #endif /* __SALVATOR_X_H */ 55