1e525d34bSNobuhiro Iwamatsu /* 2e525d34bSNobuhiro Iwamatsu * include/configs/salvator-x.h 3e525d34bSNobuhiro Iwamatsu * This file is Salvator-X board configuration. 4e525d34bSNobuhiro Iwamatsu * 5e525d34bSNobuhiro Iwamatsu * Copyright (C) 2015 Renesas Electronics Corporation 6e525d34bSNobuhiro Iwamatsu * 7e525d34bSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 8e525d34bSNobuhiro Iwamatsu */ 9e525d34bSNobuhiro Iwamatsu 10e525d34bSNobuhiro Iwamatsu #ifndef __SALVATOR_X_H 11e525d34bSNobuhiro Iwamatsu #define __SALVATOR_X_H 12e525d34bSNobuhiro Iwamatsu 13e525d34bSNobuhiro Iwamatsu #undef DEBUG 14e525d34bSNobuhiro Iwamatsu 15e525d34bSNobuhiro Iwamatsu #define CONFIG_RCAR_BOARD_STRING "Salvator-X" 16e525d34bSNobuhiro Iwamatsu 17e525d34bSNobuhiro Iwamatsu #include "rcar-gen3-common.h" 18e525d34bSNobuhiro Iwamatsu 19e525d34bSNobuhiro Iwamatsu /* SCIF */ 20e525d34bSNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 21e525d34bSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF2 22e525d34bSNobuhiro Iwamatsu #define CONFIG_CONS_INDEX 2 238474681cSMarek Vasut #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ 24e525d34bSNobuhiro Iwamatsu 25e525d34bSNobuhiro Iwamatsu /* [A] Hyper Flash */ 26e525d34bSNobuhiro Iwamatsu /* use to RPC(SPI Multi I/O Bus Controller) */ 27e525d34bSNobuhiro Iwamatsu 2890e53f8bSMarek Vasut /* Ethernet RAVB */ 2990e53f8bSMarek Vasut #define CONFIG_NET_MULTI 3090e53f8bSMarek Vasut #define CONFIG_PHY_MICREL 3190e53f8bSMarek Vasut #define CONFIG_BITBANGMII 3290e53f8bSMarek Vasut #define CONFIG_BITBANGMII_MULTI 3390e53f8bSMarek Vasut 34e525d34bSNobuhiro Iwamatsu /* Board Clock */ 35e525d34bSNobuhiro Iwamatsu /* XTAL_CLK : 33.33MHz */ 36e525d34bSNobuhiro Iwamatsu #define RCAR_XTAL_CLK 33333333u 37e525d34bSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 38e525d34bSNobuhiro Iwamatsu /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 398474681cSMarek Vasut /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ 40e525d34bSNobuhiro Iwamatsu #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 41e525d34bSNobuhiro Iwamatsu #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 42e525d34bSNobuhiro Iwamatsu #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 438474681cSMarek Vasut #define CONFIG_S3D4_CLK_FREQ (266666666u/4) 44e525d34bSNobuhiro Iwamatsu 45e525d34bSNobuhiro Iwamatsu /* Generic Timer Definitions (use in assembler source) */ 46e525d34bSNobuhiro Iwamatsu #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 47e525d34bSNobuhiro Iwamatsu 48e525d34bSNobuhiro Iwamatsu /* Generic Interrupt Controller Definitions */ 49e525d34bSNobuhiro Iwamatsu #define CONFIG_GICV2 50e525d34bSNobuhiro Iwamatsu #define GICD_BASE 0xF1010000 51e525d34bSNobuhiro Iwamatsu #define GICC_BASE 0xF1020000 52e525d34bSNobuhiro Iwamatsu 53fe2e8ff9SMarek Vasut /* i2c */ 54fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C 55fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C_SH 56fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C_SLAVE 0x60 57fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 58fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C_SH_SPEED0 400000 59fe2e8ff9SMarek Vasut #define CONFIG_SH_I2C_DATA_HIGH 4 60fe2e8ff9SMarek Vasut #define CONFIG_SH_I2C_DATA_LOW 5 61fe2e8ff9SMarek Vasut #define CONFIG_SH_I2C_CLOCK 10000000 62fe2e8ff9SMarek Vasut 63fe2e8ff9SMarek Vasut #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 64fe2e8ff9SMarek Vasut 65d1018f5fSMarek Vasut /* USB */ 66d1018f5fSMarek Vasut #ifdef CONFIG_R8A7795 67d1018f5fSMarek Vasut #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 68d1018f5fSMarek Vasut #else 69d1018f5fSMarek Vasut #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 70d1018f5fSMarek Vasut #endif 71d1018f5fSMarek Vasut 7250fb0c45SMarek Vasut /* SDHI */ 7350fb0c45SMarek Vasut #define CONFIG_SH_SDHI_FREQ 200000000 7450fb0c45SMarek Vasut 7550fb0c45SMarek Vasut /* Environment in eMMC, at the end of 2nd "boot sector" */ 7650fb0c45SMarek Vasut #define CONFIG_ENV_IS_IN_MMC 7750fb0c45SMarek Vasut #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 7850fb0c45SMarek Vasut #define CONFIG_SYS_MMC_ENV_DEV 1 7950fb0c45SMarek Vasut #define CONFIG_SYS_MMC_ENV_PART 2 8050fb0c45SMarek Vasut 81e525d34bSNobuhiro Iwamatsu /* Module stop status bits */ 82e525d34bSNobuhiro Iwamatsu /* MFIS, SCIF1 */ 83e525d34bSNobuhiro Iwamatsu #define CONFIG_SMSTP2_ENA 0x00002040 84*4c443bdbSMarek Vasut /* SCIF2 */ 85*4c443bdbSMarek Vasut #define CONFIG_SMSTP3_ENA 0x00000400 86e525d34bSNobuhiro Iwamatsu /* INTC-AP, IRQC */ 87e525d34bSNobuhiro Iwamatsu #define CONFIG_SMSTP4_ENA 0x00000180 88e525d34bSNobuhiro Iwamatsu 89e525d34bSNobuhiro Iwamatsu #endif /* __SALVATOR_X_H */ 90