1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2025 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RV1126B_COMMON_H 8 #define __CONFIG_RV1126B_COMMON_H 9 10 #define CFG_CPUID_OFFSET 0x22 11 12 #include "rockchip-common.h" 13 14 #define CONFIG_SPL_FRAMEWORK 15 #define CONFIG_SPL_TEXT_BASE 0x4fe00000 16 #define CONFIG_SPL_MAX_SIZE 0x00040000 17 #define CONFIG_SPL_BSS_START_ADDR 0x4fee0000 18 #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 19 #define CONFIG_SPL_STACK 0x4fe00000 20 #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 21 #undef CONFIG_SPL_LOAD_FIT_ADDRESS 22 #endif 23 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x42000000 24 25 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 26 #define CONFIG_SYS_CBSIZE 1024 27 28 #ifdef CONFIG_SUPPORT_USBPLUG 29 #define CONFIG_SYS_TEXT_BASE 0x40000000 30 #else 31 #define CONFIG_SYS_TEXT_BASE 0x40200000 32 #endif 33 34 #define CONFIG_SYS_INIT_SP_ADDR 0x40600000 35 #define CONFIG_SYS_LOAD_ADDR 0x40700800 36 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 37 #undef COUNTER_FREQUENCY 38 39 #define GICD_BASE 0x21201000 40 #define GICC_BASE 0x21202000 41 42 /* secure otp */ 43 #define OTP_UBOOT_ROLLBACK_OFFSET 0x310 44 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 45 #define OTP_ALL_ONES_NUM_BITS 32 46 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 47 #define OTP_SECURE_BOOT_ENABLE_SIZE 1 48 #define OTP_DISABLE_UPGRADE_ADDR 0x154 49 #define OTP_DISABLE_USB_VAL 0x3 50 #define OTP_DISABLE_SD_VAL 0xc 51 #define OTP_DISABLE_UART_VAL 0x30 52 #define OTP_DISABLE_SPI2APB_VAL 0xc0 53 #define OTP_RSA_HASH_ADDR 0x180 54 #define OTP_RSA_HASH_SIZE 32 55 #define OTP_NEXT_RSA_HASH_ADDR 0x1a0 56 #define OTP_NEXT_RSA_HASH_SIZE 32 57 #define OTP_RSA_HASH_REVOKE_VAL 0x3 58 #define OTP_RSA_HASH_REVOKE_ADDR 0x23 59 #define OTP_RSA_HASH_REVOKE_SIZE 1 60 61 /* firmware key */ 62 #define OTP_FW_ENC_KEY_ADDR (0x24 * 4) 63 #define OTP_FW_ENC_KEY_SIZE (0x04 * 4) 64 65 #define OTP_BACK_FW_ENC_KEY_ADDR (0x28 * 4) 66 #define OTP_BACK_FW_ENC_KEY_SIZE (0x04 * 4) 67 68 #define CONFIG_BOUNCE_BUFFER 69 /* For most, U-Boot no need to use 0-1G space. */ 70 #define CONFIG_SYS_SDRAM_BASE 0x40000000 71 #define SDRAM_MAX_SIZE 0xc0000000ULL /* max 3G */ 72 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1M */ 73 74 /* env used only in U-Boot */ 75 #ifndef CONFIG_SPL_BUILD 76 /* usb mass storage */ 77 #define CONFIG_USB_FUNCTION_MASS_STORAGE 78 #define CONFIG_ROCKUSB_G_DNL_PID 0x110f 79 80 #ifdef CONFIG_ARM64 81 #define ENV_MEM_LAYOUT_SETTINGS \ 82 "scriptaddr=0x40600000\0" \ 83 "pxefile_addr_r=0x40700000\0" \ 84 "fdt_addr_r=0x48300000\0" \ 85 "kernel_addr_r=0x40200000\0" \ 86 "kernel_addr_aarch32_r=0x40208000\0" \ 87 "kernel_addr_c=0x45480000\0" \ 88 "ramdisk_addr_r=0x4a200000\0" 89 #endif 90 91 #include <config_distro_bootcmd.h> 92 93 #define CONFIG_EXTRA_ENV_SETTINGS \ 94 ENV_MEM_LAYOUT_SETTINGS \ 95 "partitions=" PARTS_RKIMG \ 96 ROCKCHIP_DEVICE_SETTINGS \ 97 RKIMG_DET_BOOTDEV \ 98 BOOTENV 99 100 #undef RKIMG_BOOTCOMMAND 101 #ifdef CONFIG_FIT_SIGNATURE 102 #define RKIMG_BOOTCOMMAND \ 103 "boot_fit;" 104 #else 105 #define RKIMG_BOOTCOMMAND \ 106 "boot_fit;" \ 107 "boot_android ${devtype} ${devnum};" 108 #endif 109 #endif /* !CONFIG_SPL_BUILD */ 110 111 #if defined(CONFIG_USB_HOST) || defined(CONFIG_SPL_USB_HOST_SUPPORT) 112 /* rockchip ohci host driver */ 113 #define CONFIG_USB_OHCI_NEW 114 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 115 #endif 116 117 #define CONFIG_PREBOOT 118 #define CONFIG_LIB_HW_RAND 119 120 #endif /* __CONFIG_RV1126B_COMMON_H */ 121