1*4e72b326SXuhui Lin /* SPDX-License-Identifier: GPL-2.0+ */ 2*4e72b326SXuhui Lin /* 3*4e72b326SXuhui Lin * (C) Copyright 2025 Rockchip Electronics Co., Ltd 4*4e72b326SXuhui Lin * 5*4e72b326SXuhui Lin */ 6*4e72b326SXuhui Lin 7*4e72b326SXuhui Lin #ifndef __CONFIG_RV1126B_COMMON_H 8*4e72b326SXuhui Lin #define __CONFIG_RV1126B_COMMON_H 9*4e72b326SXuhui Lin 10*4e72b326SXuhui Lin #define CFG_CPUID_OFFSET 0x22 11*4e72b326SXuhui Lin 12*4e72b326SXuhui Lin #include "rockchip-common.h" 13*4e72b326SXuhui Lin 14*4e72b326SXuhui Lin #define CONFIG_SPL_FRAMEWORK 15*4e72b326SXuhui Lin #define CONFIG_SPL_TEXT_BASE 0x43f00000 16*4e72b326SXuhui Lin #define CONFIG_SPL_MAX_SIZE 0x00040000 17*4e72b326SXuhui Lin #define CONFIG_SPL_BSS_START_ADDR 0x43fe0000 18*4e72b326SXuhui Lin #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 19*4e72b326SXuhui Lin #define CONFIG_SPL_STACK 0x43f00000 20*4e72b326SXuhui Lin #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 21*4e72b326SXuhui Lin #undef CONFIG_SPL_LOAD_FIT_ADDRESS 22*4e72b326SXuhui Lin #endif 23*4e72b326SXuhui Lin #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x42000000 24*4e72b326SXuhui Lin 25*4e72b326SXuhui Lin #define CONFIG_SYS_MALLOC_LEN (32 << 20) 26*4e72b326SXuhui Lin #define CONFIG_SYS_CBSIZE 1024 27*4e72b326SXuhui Lin 28*4e72b326SXuhui Lin #ifdef CONFIG_SUPPORT_USBPLUG 29*4e72b326SXuhui Lin #define CONFIG_SYS_TEXT_BASE 0x40000000 30*4e72b326SXuhui Lin #else 31*4e72b326SXuhui Lin #define CONFIG_SYS_TEXT_BASE 0x40200000 32*4e72b326SXuhui Lin #endif 33*4e72b326SXuhui Lin 34*4e72b326SXuhui Lin #define CONFIG_SYS_INIT_SP_ADDR 0x40600000 35*4e72b326SXuhui Lin #define CONFIG_SYS_LOAD_ADDR 0x40700800 36*4e72b326SXuhui Lin #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 37*4e72b326SXuhui Lin 38*4e72b326SXuhui Lin #define GICD_BASE 0x21201000 39*4e72b326SXuhui Lin #define GICC_BASE 0x21202000 40*4e72b326SXuhui Lin 41*4e72b326SXuhui Lin #define CONFIG_BOUNCE_BUFFER 42*4e72b326SXuhui Lin /* For most, U-Boot no need to use 0-1G space. */ 43*4e72b326SXuhui Lin #define CONFIG_SYS_SDRAM_BASE 0x40000000 44*4e72b326SXuhui Lin #define SDRAM_MAX_SIZE 0xc0000000ULL /* max 3G */ 45*4e72b326SXuhui Lin #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1M */ 46*4e72b326SXuhui Lin 47*4e72b326SXuhui Lin /* env used only in U-Boot */ 48*4e72b326SXuhui Lin #ifndef CONFIG_SPL_BUILD 49*4e72b326SXuhui Lin /* usb mass storage */ 50*4e72b326SXuhui Lin #define CONFIG_USB_FUNCTION_MASS_STORAGE 51*4e72b326SXuhui Lin #define CONFIG_ROCKUSB_G_DNL_PID 0x110f 52*4e72b326SXuhui Lin 53*4e72b326SXuhui Lin #ifdef CONFIG_ARM64 54*4e72b326SXuhui Lin #define ENV_MEM_LAYOUT_SETTINGS \ 55*4e72b326SXuhui Lin "scriptaddr=0x40600000\0" \ 56*4e72b326SXuhui Lin "pxefile_addr_r=0x40700000\0" \ 57*4e72b326SXuhui Lin "fdt_addr_r=0x48300000\0" \ 58*4e72b326SXuhui Lin "kernel_addr_r=0x40400000\0" \ 59*4e72b326SXuhui Lin "kernel_addr_c=0x45480000\0" \ 60*4e72b326SXuhui Lin "ramdisk_addr_r=0x4a200000\0" 61*4e72b326SXuhui Lin #else 62*4e72b326SXuhui Lin #define ENV_MEM_LAYOUT_SETTINGS \ 63*4e72b326SXuhui Lin "scriptaddr=0x40600000\0" \ 64*4e72b326SXuhui Lin "pxefile_addr_r=0x40700000\0" \ 65*4e72b326SXuhui Lin "fdt_addr_r=0x48300000\0" \ 66*4e72b326SXuhui Lin "kernel_addr_r=0x40208000\0" \ 67*4e72b326SXuhui Lin "kernel_addr_c=0x41200000\0" \ 68*4e72b326SXuhui Lin "ramdisk_addr_r=0x41800000\0" 69*4e72b326SXuhui Lin #endif 70*4e72b326SXuhui Lin 71*4e72b326SXuhui Lin #include <config_distro_bootcmd.h> 72*4e72b326SXuhui Lin 73*4e72b326SXuhui Lin #define CONFIG_EXTRA_ENV_SETTINGS \ 74*4e72b326SXuhui Lin ENV_MEM_LAYOUT_SETTINGS \ 75*4e72b326SXuhui Lin "partitions=" PARTS_RKIMG \ 76*4e72b326SXuhui Lin ROCKCHIP_DEVICE_SETTINGS \ 77*4e72b326SXuhui Lin RKIMG_DET_BOOTDEV \ 78*4e72b326SXuhui Lin BOOTENV 79*4e72b326SXuhui Lin 80*4e72b326SXuhui Lin #undef RKIMG_BOOTCOMMAND 81*4e72b326SXuhui Lin #ifdef CONFIG_FIT_SIGNATURE 82*4e72b326SXuhui Lin #define RKIMG_BOOTCOMMAND \ 83*4e72b326SXuhui Lin "boot_fit;" 84*4e72b326SXuhui Lin #else 85*4e72b326SXuhui Lin #define RKIMG_BOOTCOMMAND \ 86*4e72b326SXuhui Lin "boot_fit;" \ 87*4e72b326SXuhui Lin "boot_android ${devtype} ${devnum};" 88*4e72b326SXuhui Lin #endif 89*4e72b326SXuhui Lin #endif /* !CONFIG_SPL_BUILD */ 90*4e72b326SXuhui Lin 91*4e72b326SXuhui Lin /* rockchip ohci host driver */ 92*4e72b326SXuhui Lin #define CONFIG_USB_OHCI_NEW 93*4e72b326SXuhui Lin #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 94*4e72b326SXuhui Lin 95*4e72b326SXuhui Lin #define CONFIG_PREBOOT 96*4e72b326SXuhui Lin #define CONFIG_LIB_HW_RAND 97*4e72b326SXuhui Lin 98*4e72b326SXuhui Lin #endif /* __CONFIG_RV1126B_COMMON_H */ 99