12c1e11ddSAndy Yan /* 22c1e11ddSAndy Yan * (C) Copyright 2016 Rockchip Electronics Co., Ltd 32c1e11ddSAndy Yan * 42c1e11ddSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 52c1e11ddSAndy Yan */ 62c1e11ddSAndy Yan #ifndef __CONFIG_RV1108_COMMON_H 72c1e11ddSAndy Yan #define __CONFIG_RV1108_COMMON_H 82c1e11ddSAndy Yan 92c1e11ddSAndy Yan #include <asm/arch/hardware.h> 102c1e11ddSAndy Yan #include "rockchip-common.h" 112c1e11ddSAndy Yan 122c1e11ddSAndy Yan #define CONFIG_SYS_MALLOC_LEN (32 << 20) 132c1e11ddSAndy Yan #define CONFIG_SYS_CBSIZE 1024 142c1e11ddSAndy Yan #define CONFIG_SKIP_LOWLEVEL_INIT 152c1e11ddSAndy Yan 162c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 172c1e11ddSAndy Yan /* TIMER1,initialized by ddr initialize code */ 182c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_BASE 0x10350020 192c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 202c1e11ddSAndy Yan 212c1e11ddSAndy Yan #define CONFIG_SYS_NS16550 222c1e11ddSAndy Yan #define CONFIG_SYS_NS16550_MEM32 232c1e11ddSAndy Yan 242c1e11ddSAndy Yan #define CONFIG_SYS_SDRAM_BASE 0x60000000 252c1e11ddSAndy Yan #define CONFIG_NR_DRAM_BANKS 1 262c1e11ddSAndy Yan #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE 272c1e11ddSAndy Yan #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) 282c1e11ddSAndy Yan #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) 292c1e11ddSAndy Yan 30*8f3e6817SFrank Wang /* usb mass storage */ 31*8f3e6817SFrank Wang #define CONFIG_USB_FUNCTION_MASS_STORAGE 32*8f3e6817SFrank Wang 3331d551b6SWilliam Wu /* rockchip ohci host driver */ 3431d551b6SWilliam Wu #define CONFIG_USB_OHCI_NEW 3531d551b6SWilliam Wu #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 362c1e11ddSAndy Yan #endif 37