12c1e11ddSAndy Yan /* 22c1e11ddSAndy Yan * (C) Copyright 2016 Rockchip Electronics Co., Ltd 32c1e11ddSAndy Yan * 42c1e11ddSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 52c1e11ddSAndy Yan */ 62c1e11ddSAndy Yan #ifndef __CONFIG_RV1108_COMMON_H 72c1e11ddSAndy Yan #define __CONFIG_RV1108_COMMON_H 82c1e11ddSAndy Yan 92c1e11ddSAndy Yan #include <asm/arch/hardware.h> 102c1e11ddSAndy Yan #include "rockchip-common.h" 112c1e11ddSAndy Yan 122c1e11ddSAndy Yan #define CONFIG_SYS_MALLOC_LEN (32 << 20) 132c1e11ddSAndy Yan #define CONFIG_SYS_CBSIZE 1024 142c1e11ddSAndy Yan #define CONFIG_SKIP_LOWLEVEL_INIT 152c1e11ddSAndy Yan 162c1e11ddSAndy Yan #define CONFIG_SYS_SDRAM_BASE 0x60000000 17*52f7b21dSZhihuan He #define SDRAM_MAX_SIZE 0x80000000 182c1e11ddSAndy Yan #define CONFIG_NR_DRAM_BANKS 1 192c1e11ddSAndy Yan #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE 202c1e11ddSAndy Yan #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) 212c1e11ddSAndy Yan #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) 222c1e11ddSAndy Yan 23*52f7b21dSZhihuan He /* SPL support */ 24*52f7b21dSZhihuan He #define CONFIG_SPL_STACK 0x10080700 25*52f7b21dSZhihuan He #define CONFIG_SPL_TEXT_BASE 0x10080800 26*52f7b21dSZhihuan He #define CONFIG_SPL_MAX_SIZE 0x1700 27*52f7b21dSZhihuan He 28*52f7b21dSZhihuan He /* BSS setup */ 29*52f7b21dSZhihuan He #define CONFIG_SPL_BSS_MAX_SIZE 0x100 30*52f7b21dSZhihuan He 31ba437c8cSFrank Wang #define CONFIG_ROCKUSB_G_DNL_PID 0x110A 32ba437c8cSFrank Wang 33058af259SAndy Yan #define CONFIG_BOUNCE_BUFFER 34058af259SAndy Yan 358f3e6817SFrank Wang /* usb mass storage */ 368f3e6817SFrank Wang #define CONFIG_USB_FUNCTION_MASS_STORAGE 378f3e6817SFrank Wang 3831d551b6SWilliam Wu /* rockchip ohci host driver */ 3931d551b6SWilliam Wu #define CONFIG_USB_OHCI_NEW 4031d551b6SWilliam Wu #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 412c1e11ddSAndy Yan #endif 42