1*2c1e11ddSAndy Yan /* 2*2c1e11ddSAndy Yan * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*2c1e11ddSAndy Yan * 4*2c1e11ddSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 5*2c1e11ddSAndy Yan */ 6*2c1e11ddSAndy Yan #ifndef __CONFIG_RV1108_COMMON_H 7*2c1e11ddSAndy Yan #define __CONFIG_RV1108_COMMON_H 8*2c1e11ddSAndy Yan 9*2c1e11ddSAndy Yan #include <asm/arch/hardware.h> 10*2c1e11ddSAndy Yan #include "rockchip-common.h" 11*2c1e11ddSAndy Yan 12*2c1e11ddSAndy Yan #define CONFIG_ENV_IS_NOWHERE 13*2c1e11ddSAndy Yan #define CONFIG_ENV_SIZE 0x2000 14*2c1e11ddSAndy Yan #define CONFIG_SYS_MAXARGS 16 15*2c1e11ddSAndy Yan #define CONFIG_SYS_MALLOC_LEN (32 << 20) 16*2c1e11ddSAndy Yan #define CONFIG_SYS_CBSIZE 1024 17*2c1e11ddSAndy Yan #define CONFIG_SKIP_LOWLEVEL_INIT 18*2c1e11ddSAndy Yan 19*2c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 20*2c1e11ddSAndy Yan /* TIMER1,initialized by ddr initialize code */ 21*2c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_BASE 0x10350020 22*2c1e11ddSAndy Yan #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 23*2c1e11ddSAndy Yan 24*2c1e11ddSAndy Yan #define CONFIG_SYS_NS16550 25*2c1e11ddSAndy Yan #define CONFIG_SYS_NS16550_MEM32 26*2c1e11ddSAndy Yan 27*2c1e11ddSAndy Yan #define CONFIG_SYS_SDRAM_BASE 0x60000000 28*2c1e11ddSAndy Yan #define CONFIG_NR_DRAM_BANKS 1 29*2c1e11ddSAndy Yan #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE 30*2c1e11ddSAndy Yan #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) 31*2c1e11ddSAndy Yan #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) 32*2c1e11ddSAndy Yan 33*2c1e11ddSAndy Yan #endif 34