1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK3588_COMMON_H 8 #define __CONFIG_RK3588_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SPL_FRAMEWORK 13 #define CONFIG_SPL_TEXT_BASE 0x00000000 14 #define CONFIG_SPL_MAX_SIZE 0x00040000 15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17 #define CONFIG_SPL_STACK 0x03fe0000 18 #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 19 #undef CONFIG_SPL_LOAD_FIT_ADDRESS 20 #endif 21 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 22 23 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 24 #define CONFIG_SYS_CBSIZE 1024 25 #define CONFIG_SKIP_LOWLEVEL_INIT 26 27 #ifdef CONFIG_SUPPORT_USBPLUG 28 #define CONFIG_SYS_TEXT_BASE 0x00000000 29 #else 30 #define CONFIG_SYS_TEXT_BASE 0x00200000 31 #endif 32 33 #define CONFIG_SYS_INIT_SP_ADDR 0x00600000 34 #define CONFIG_SYS_LOAD_ADDR 0x00600800 35 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 36 #define COUNTER_FREQUENCY 24000000 37 38 #define GICD_BASE 0xfe600000 39 #define GICR_BASE 0xfe680000 40 #define GICC_BASE 0xfe600000 41 42 /* secure otp */ 43 #define OTP_UBOOT_ROLLBACK_OFFSET 0x150 44 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 45 #define OTP_ALL_ONES_NUM_BITS 32 46 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 47 #define OTP_SECURE_BOOT_ENABLE_SIZE 1 48 #define OTP_RSA4096_ENABLE_ADDR 0x21 49 #define OTP_RSA4096_ENABLE_SIZE 1 50 #define OTP_RSA_HASH_ADDR 0x9c0 51 #define OTP_RSA_HASH_SIZE 32 52 53 /* MMC/SD IP block */ 54 #define CONFIG_BOUNCE_BUFFER 55 56 #define CONFIG_SYS_SDRAM_BASE 0 57 #define SDRAM_MAX_SIZE 0xf0000000 58 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 59 60 #ifndef CONFIG_SPL_BUILD 61 /* usb mass storage */ 62 #define CONFIG_USB_FUNCTION_MASS_STORAGE 63 #define CONFIG_ROCKUSB_G_DNL_PID 0x350b 64 #define ROCKUSB_FSG_BUFLEN 0x400000 65 66 /* Nand */ 67 #define CONFIG_SYS_NAND_BASE 0 68 #define CONFIG_SYS_MAX_NAND_DEVICE 1 69 #define CONFIG_SYS_NAND_ONFI_DETECTION 70 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 71 #define CONFIG_SYS_NAND_PAGE_COUNT 64 72 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 73 74 /* 75 * decompressed kernel: 4M ~ 84M 76 * Why not start from 2M ? if kernel < 5.10 in Android image, 77 * the image header will use the 0x180000~0x200000, which is 78 * overlap with share memory region 0x100000~0x200000. 79 * 80 * compressed kernel: 84M ~ 130M 81 */ 82 #define ENV_MEM_LAYOUT_SETTINGS \ 83 "scriptaddr=0x00500000\0" \ 84 "pxefile_addr_r=0x00600000\0" \ 85 "fdt_addr_r=0x08300000\0" \ 86 "kernel_addr_r=0x00400000\0" \ 87 "kernel_addr_c=0x05480000\0" \ 88 "ramdisk_addr_r=0x0a200000\0" 89 90 #include <config_distro_bootcmd.h> 91 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 BOOTENV_SHARED_MTD \ 94 ENV_MEM_LAYOUT_SETTINGS \ 95 "partitions=" PARTS_RKIMG \ 96 ROCKCHIP_DEVICE_SETTINGS \ 97 RKIMG_DET_BOOTDEV \ 98 BOOTENV 99 #endif 100 101 /* rockchip ohci host driver */ 102 #define CONFIG_USB_OHCI_NEW 103 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 104 105 #define CONFIG_PREBOOT 106 #define CONFIG_LIB_HW_RAND 107 108 #endif 109