1*e1cfe1c9SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*e1cfe1c9SJoseph Chen /* 3*e1cfe1c9SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd 4*e1cfe1c9SJoseph Chen * 5*e1cfe1c9SJoseph Chen */ 6*e1cfe1c9SJoseph Chen 7*e1cfe1c9SJoseph Chen #ifndef __CONFIG_RK3588_COMMON_H 8*e1cfe1c9SJoseph Chen #define __CONFIG_RK3588_COMMON_H 9*e1cfe1c9SJoseph Chen 10*e1cfe1c9SJoseph Chen #include "rockchip-common.h" 11*e1cfe1c9SJoseph Chen 12*e1cfe1c9SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13*e1cfe1c9SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14*e1cfe1c9SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 15*e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17*e1cfe1c9SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 18*e1cfe1c9SJoseph Chen 19*e1cfe1c9SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*e1cfe1c9SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21*e1cfe1c9SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22*e1cfe1c9SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 23*e1cfe1c9SJoseph Chen 24*e1cfe1c9SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 25*e1cfe1c9SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00400800 26*e1cfe1c9SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 27*e1cfe1c9SJoseph Chen #define COUNTER_FREQUENCY 24000000 28*e1cfe1c9SJoseph Chen 29*e1cfe1c9SJoseph Chen #define GICD_BASE 0xfe600000 30*e1cfe1c9SJoseph Chen #define GICR_BASE 0xfe680000 31*e1cfe1c9SJoseph Chen #define GICC_BASE 0xfe600000 32*e1cfe1c9SJoseph Chen 33*e1cfe1c9SJoseph Chen /* MMC/SD IP block */ 34*e1cfe1c9SJoseph Chen #define CONFIG_BOUNCE_BUFFER 35*e1cfe1c9SJoseph Chen 36*e1cfe1c9SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 37*e1cfe1c9SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 38*e1cfe1c9SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 39*e1cfe1c9SJoseph Chen 40*e1cfe1c9SJoseph Chen #ifndef CONFIG_SPL_BUILD 41*e1cfe1c9SJoseph Chen /* usb mass storage */ 42*e1cfe1c9SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 43*e1cfe1c9SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350b 44*e1cfe1c9SJoseph Chen 45*e1cfe1c9SJoseph Chen /* 46*e1cfe1c9SJoseph Chen * decompressed kernel: 4M ~ 84M 47*e1cfe1c9SJoseph Chen * compressed kernel: 84M ~ 131M 48*e1cfe1c9SJoseph Chen */ 49*e1cfe1c9SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 50*e1cfe1c9SJoseph Chen "scriptaddr=0x00500000\0" \ 51*e1cfe1c9SJoseph Chen "pxefile_addr_r=0x00600000\0" \ 52*e1cfe1c9SJoseph Chen "fdt_addr_r=0x0a100000\0" \ 53*e1cfe1c9SJoseph Chen "kernel_addr_r=0x00400000\0" \ 54*e1cfe1c9SJoseph Chen "kernel_addr_c=0x05480000\0" \ 55*e1cfe1c9SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 56*e1cfe1c9SJoseph Chen 57*e1cfe1c9SJoseph Chen #include <config_distro_bootcmd.h> 58*e1cfe1c9SJoseph Chen 59*e1cfe1c9SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 60*e1cfe1c9SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 61*e1cfe1c9SJoseph Chen "partitions=" PARTS_RKIMG \ 62*e1cfe1c9SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 63*e1cfe1c9SJoseph Chen RKIMG_DET_BOOTDEV \ 64*e1cfe1c9SJoseph Chen BOOTENV 65*e1cfe1c9SJoseph Chen 66*e1cfe1c9SJoseph Chen #undef RKIMG_BOOTCOMMAND 67*e1cfe1c9SJoseph Chen #define RKIMG_BOOTCOMMAND \ 68*e1cfe1c9SJoseph Chen "boot_fit;" \ 69*e1cfe1c9SJoseph Chen "boot_android ${devtype} ${devnum};" \ 70*e1cfe1c9SJoseph Chen "run distro_bootcmd;" 71*e1cfe1c9SJoseph Chen #endif 72*e1cfe1c9SJoseph Chen 73*e1cfe1c9SJoseph Chen /* rockchip ohci host driver */ 74*e1cfe1c9SJoseph Chen #define CONFIG_USB_OHCI_NEW 75*e1cfe1c9SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 76*e1cfe1c9SJoseph Chen 77*e1cfe1c9SJoseph Chen #define CONFIG_PREBOOT 78*e1cfe1c9SJoseph Chen #define CONFIG_LIB_HW_RAND 79*e1cfe1c9SJoseph Chen 80*e1cfe1c9SJoseph Chen #endif 81