1e1cfe1c9SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2e1cfe1c9SJoseph Chen /* 3e1cfe1c9SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd 4e1cfe1c9SJoseph Chen * 5e1cfe1c9SJoseph Chen */ 6e1cfe1c9SJoseph Chen 7e1cfe1c9SJoseph Chen #ifndef __CONFIG_RK3588_COMMON_H 8e1cfe1c9SJoseph Chen #define __CONFIG_RK3588_COMMON_H 9e1cfe1c9SJoseph Chen 10e1cfe1c9SJoseph Chen #include "rockchip-common.h" 11e1cfe1c9SJoseph Chen 12e1cfe1c9SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13e1cfe1c9SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14e1cfe1c9SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 15e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17e1cfe1c9SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 18e1cfe1c9SJoseph Chen 19e1cfe1c9SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20e1cfe1c9SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21e1cfe1c9SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22e1cfe1c9SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 23e1cfe1c9SJoseph Chen 24e1cfe1c9SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 25e1cfe1c9SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00400800 26e1cfe1c9SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 27e1cfe1c9SJoseph Chen #define COUNTER_FREQUENCY 24000000 28e1cfe1c9SJoseph Chen 29e1cfe1c9SJoseph Chen #define GICD_BASE 0xfe600000 30e1cfe1c9SJoseph Chen #define GICR_BASE 0xfe680000 31e1cfe1c9SJoseph Chen #define GICC_BASE 0xfe600000 32e1cfe1c9SJoseph Chen 339730632aSJason Zhu /* secure otp */ 349730632aSJason Zhu #define OTP_UBOOT_ROLLBACK_OFFSET 0x150 359730632aSJason Zhu #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 369730632aSJason Zhu #define OTP_ALL_ONES_NUM_BITS 32 379730632aSJason Zhu #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 389730632aSJason Zhu #define OTP_SECURE_BOOT_ENABLE_SIZE 1 399730632aSJason Zhu #define OTP_RSA_HASH_ADDR 0x9c0 409730632aSJason Zhu #define OTP_RSA_HASH_SIZE 32 419730632aSJason Zhu 42e1cfe1c9SJoseph Chen /* MMC/SD IP block */ 43e1cfe1c9SJoseph Chen #define CONFIG_BOUNCE_BUFFER 44e1cfe1c9SJoseph Chen 45e1cfe1c9SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 46e1cfe1c9SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 47e1cfe1c9SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 48e1cfe1c9SJoseph Chen 49e1cfe1c9SJoseph Chen #ifndef CONFIG_SPL_BUILD 50e1cfe1c9SJoseph Chen /* usb mass storage */ 51e1cfe1c9SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 52e1cfe1c9SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350b 53e1cfe1c9SJoseph Chen 54e1cfe1c9SJoseph Chen /* 55e1cfe1c9SJoseph Chen * decompressed kernel: 4M ~ 84M 56e1cfe1c9SJoseph Chen * compressed kernel: 84M ~ 131M 57e1cfe1c9SJoseph Chen */ 58e1cfe1c9SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 59e1cfe1c9SJoseph Chen "scriptaddr=0x00500000\0" \ 60e1cfe1c9SJoseph Chen "pxefile_addr_r=0x00600000\0" \ 61e1cfe1c9SJoseph Chen "fdt_addr_r=0x0a100000\0" \ 62e1cfe1c9SJoseph Chen "kernel_addr_r=0x00400000\0" \ 63e1cfe1c9SJoseph Chen "kernel_addr_c=0x05480000\0" \ 64e1cfe1c9SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 65e1cfe1c9SJoseph Chen 66e1cfe1c9SJoseph Chen #include <config_distro_bootcmd.h> 67e1cfe1c9SJoseph Chen 68e1cfe1c9SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 69*3f10ff45SJoseph Chen BOOTENV_SHARED_MTD \ 70e1cfe1c9SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 71e1cfe1c9SJoseph Chen "partitions=" PARTS_RKIMG \ 72e1cfe1c9SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 73e1cfe1c9SJoseph Chen RKIMG_DET_BOOTDEV \ 74e1cfe1c9SJoseph Chen BOOTENV 75e1cfe1c9SJoseph Chen #endif 76e1cfe1c9SJoseph Chen 77e1cfe1c9SJoseph Chen /* rockchip ohci host driver */ 78e1cfe1c9SJoseph Chen #define CONFIG_USB_OHCI_NEW 79e1cfe1c9SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 80e1cfe1c9SJoseph Chen 81e1cfe1c9SJoseph Chen #define CONFIG_PREBOOT 82e1cfe1c9SJoseph Chen #define CONFIG_LIB_HW_RAND 83e1cfe1c9SJoseph Chen 84e1cfe1c9SJoseph Chen #endif 85