1e1cfe1c9SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2e1cfe1c9SJoseph Chen /* 3e1cfe1c9SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd 4e1cfe1c9SJoseph Chen * 5e1cfe1c9SJoseph Chen */ 6e1cfe1c9SJoseph Chen 7e1cfe1c9SJoseph Chen #ifndef __CONFIG_RK3588_COMMON_H 8e1cfe1c9SJoseph Chen #define __CONFIG_RK3588_COMMON_H 9e1cfe1c9SJoseph Chen 10e1cfe1c9SJoseph Chen #include "rockchip-common.h" 11e1cfe1c9SJoseph Chen 12e1cfe1c9SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13e1cfe1c9SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14e1cfe1c9SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 15e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16e1cfe1c9SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17e1cfe1c9SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 184c8e468bSKever Yang #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 194c8e468bSKever Yang #undef CONFIG_SPL_LOAD_FIT_ADDRESS 204c8e468bSKever Yang #endif 214c8e468bSKever Yang #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 22e1cfe1c9SJoseph Chen 23e1cfe1c9SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 24e1cfe1c9SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 25e1cfe1c9SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 26e8bd6640SYifeng Zhao 27e8bd6640SYifeng Zhao #ifdef CONFIG_SUPPORT_USBPLUG 28e8bd6640SYifeng Zhao #define CONFIG_SYS_TEXT_BASE 0x00000000 29e8bd6640SYifeng Zhao #else 30c63c8539SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 31e8bd6640SYifeng Zhao #endif 32e1cfe1c9SJoseph Chen 3377ed6a2bSJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00600000 3477ed6a2bSJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00600800 35e1cfe1c9SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 36e1cfe1c9SJoseph Chen #define COUNTER_FREQUENCY 24000000 37e1cfe1c9SJoseph Chen 38e1cfe1c9SJoseph Chen #define GICD_BASE 0xfe600000 39e1cfe1c9SJoseph Chen #define GICR_BASE 0xfe680000 40e1cfe1c9SJoseph Chen #define GICC_BASE 0xfe600000 41e1cfe1c9SJoseph Chen 429730632aSJason Zhu /* secure otp */ 439730632aSJason Zhu #define OTP_UBOOT_ROLLBACK_OFFSET 0x150 449730632aSJason Zhu #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 459730632aSJason Zhu #define OTP_ALL_ONES_NUM_BITS 32 469730632aSJason Zhu #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 479730632aSJason Zhu #define OTP_SECURE_BOOT_ENABLE_SIZE 1 488e379471SXuhui Lin #define OTP_RSA4096_ENABLE_ADDR 0x21 498e379471SXuhui Lin #define OTP_RSA4096_ENABLE_SIZE 1 509730632aSJason Zhu #define OTP_RSA_HASH_ADDR 0x9c0 519730632aSJason Zhu #define OTP_RSA_HASH_SIZE 32 529730632aSJason Zhu 53e1cfe1c9SJoseph Chen /* MMC/SD IP block */ 54e1cfe1c9SJoseph Chen #define CONFIG_BOUNCE_BUFFER 55e1cfe1c9SJoseph Chen 56e1cfe1c9SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 57e1cfe1c9SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 58e1cfe1c9SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 59e1cfe1c9SJoseph Chen 60e1cfe1c9SJoseph Chen #ifndef CONFIG_SPL_BUILD 61e1cfe1c9SJoseph Chen /* usb mass storage */ 62e1cfe1c9SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 63e1cfe1c9SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350b 6425f87300SWilliam Wu #define ROCKUSB_FSG_BUFLEN 0x400000 65e1cfe1c9SJoseph Chen 66*b1aae50aSJon Lin /* Nand */ 67*b1aae50aSJon Lin #define CONFIG_SYS_NAND_BASE 0 68*b1aae50aSJon Lin #define CONFIG_SYS_MAX_NAND_DEVICE 1 69*b1aae50aSJon Lin #define CONFIG_SYS_NAND_ONFI_DETECTION 70*b1aae50aSJon Lin #define CONFIG_SYS_NAND_PAGE_SIZE 2048 71*b1aae50aSJon Lin #define CONFIG_SYS_NAND_PAGE_COUNT 64 72*b1aae50aSJon Lin #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 73*b1aae50aSJon Lin 74e1cfe1c9SJoseph Chen /* 75e1cfe1c9SJoseph Chen * decompressed kernel: 4M ~ 84M 763ee684f1SJoseph Chen * Why not start from 2M ? if kernel < 5.10 in Android image, 773ee684f1SJoseph Chen * the image header will use the 0x180000~0x200000, which is 783ee684f1SJoseph Chen * overlap with share memory region 0x100000~0x200000. 793ee684f1SJoseph Chen * 80bad05d5cSJoseph Chen * compressed kernel: 84M ~ 130M 81e1cfe1c9SJoseph Chen */ 82e1cfe1c9SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 83e1cfe1c9SJoseph Chen "scriptaddr=0x00500000\0" \ 84e1cfe1c9SJoseph Chen "pxefile_addr_r=0x00600000\0" \ 85bad05d5cSJoseph Chen "fdt_addr_r=0x08300000\0" \ 86e1cfe1c9SJoseph Chen "kernel_addr_r=0x00400000\0" \ 87e1cfe1c9SJoseph Chen "kernel_addr_c=0x05480000\0" \ 88e1cfe1c9SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 89e1cfe1c9SJoseph Chen 90e1cfe1c9SJoseph Chen #include <config_distro_bootcmd.h> 91e1cfe1c9SJoseph Chen 92e1cfe1c9SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 933f10ff45SJoseph Chen BOOTENV_SHARED_MTD \ 94e1cfe1c9SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 95e1cfe1c9SJoseph Chen "partitions=" PARTS_RKIMG \ 96e1cfe1c9SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 97e1cfe1c9SJoseph Chen RKIMG_DET_BOOTDEV \ 98e1cfe1c9SJoseph Chen BOOTENV 99e1cfe1c9SJoseph Chen #endif 100e1cfe1c9SJoseph Chen 101e1cfe1c9SJoseph Chen /* rockchip ohci host driver */ 102e1cfe1c9SJoseph Chen #define CONFIG_USB_OHCI_NEW 103e1cfe1c9SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 104e1cfe1c9SJoseph Chen 105e1cfe1c9SJoseph Chen #define CONFIG_PREBOOT 106e1cfe1c9SJoseph Chen #define CONFIG_LIB_HW_RAND 107e1cfe1c9SJoseph Chen 108e1cfe1c9SJoseph Chen #endif 109