1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2023 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK3576_COMMON_H 8 #define __CONFIG_RK3576_COMMON_H 9 10 #define CFG_CPUID_OFFSET 0xa 11 12 #include "rockchip-common.h" 13 14 #define CONFIG_SPL_FRAMEWORK 15 #define CONFIG_SPL_TEXT_BASE 0x40000000 16 #define CONFIG_SPL_MAX_SIZE 0x00060000 17 #define CONFIG_SPL_BSS_START_ADDR 0x43fe0000 18 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 19 #define CONFIG_SPL_STACK 0x43fe0000 20 #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 21 #undef CONFIG_SPL_LOAD_FIT_ADDRESS 22 #endif 23 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x42000000 24 25 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 26 #define CONFIG_SYS_CBSIZE 1024 27 28 #ifdef CONFIG_SUPPORT_USBPLUG 29 #define CONFIG_SYS_TEXT_BASE 0x40000000 30 #else 31 #define CONFIG_SYS_TEXT_BASE 0x40200000 32 #endif 33 34 #define CONFIG_SYS_INIT_SP_ADDR 0x40600000 35 #define CONFIG_SYS_LOAD_ADDR 0x40700800 36 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 37 #undef COUNTER_FREQUENCY 38 39 #define GICD_BASE 0x2a701000 40 #define GICC_BASE 0x2a702000 41 42 /* secure otp */ 43 #define OTP_UBOOT_ROLLBACK_OFFSET 0x610 44 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 45 #define OTP_ALL_ONES_NUM_BITS 32 46 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 47 #define OTP_SECURE_BOOT_ENABLE_SIZE 1 48 #define OTP_RSA4096_ENABLE_ADDR 0x21 49 #define OTP_RSA4096_ENABLE_SIZE 1 50 #define OTP_RSA_HASH_ADDR 0x200 51 #define OTP_RSA_HASH_SIZE 32 52 53 #define CONFIG_BOUNCE_BUFFER 54 #define CONFIG_SYS_SDRAM_BASE 0x40000000 55 #define SDRAM_MAX_SIZE (0x100000000 - CONFIG_SYS_SDRAM_BASE) /* max 4G */ 56 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1M */ 57 58 #if CONFIG_IS_ENABLED(SMP) 59 #define SMP_CPU0 0x0 60 #define SMP_CPU1 0x1 61 #define SMP_CPU2 0x2 62 #define SMP_CORE_ADDR 0x48200000 63 #define SMP_CPU1_STACK 0x48200000 64 #define SMP_CPU2_STACK 0x48180000 65 #endif 66 67 /* env used only in U-Boot */ 68 #ifndef CONFIG_SPL_BUILD 69 /* usb mass storage */ 70 #define CONFIG_USB_FUNCTION_MASS_STORAGE 71 #define CONFIG_ROCKUSB_G_DNL_PID 0x350e 72 73 /* 74 * DDR layout mainly follow rk3588 Soc 75 */ 76 #define ENV_MEM_LAYOUT_SETTINGS \ 77 "scriptaddr=0x40500000\0" \ 78 "pxefile_addr_r=0x40600000\0" \ 79 "fdt_addr_r=0x48300000\0" \ 80 "kernel_addr_r=0x40400000\0" \ 81 "kernel_addr_c=0x45480000\0" \ 82 "ramdisk_addr_r=0x4a200000\0" 83 84 #include <config_distro_bootcmd.h> 85 86 #define CONFIG_EXTRA_ENV_SETTINGS \ 87 ENV_MEM_LAYOUT_SETTINGS \ 88 "partitions=" PARTS_RKIMG \ 89 ROCKCHIP_DEVICE_SETTINGS \ 90 RKIMG_DET_BOOTDEV \ 91 BOOTENV 92 #endif /* !CONFIG_SPL_BUILD */ 93 94 /* rockchip ohci host driver */ 95 #define CONFIG_USB_OHCI_NEW 96 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 97 98 #define CONFIG_PREBOOT 99 #define CONFIG_LIB_HW_RAND 100 101 #endif /* __CONFIG_RK3576_COMMON_H */ 102