1bf72c9c9SXuhui Lin /* SPDX-License-Identifier: GPL-2.0+ */ 2bf72c9c9SXuhui Lin /* 3bf72c9c9SXuhui Lin * (C) Copyright 2023 Rockchip Electronics Co., Ltd 4bf72c9c9SXuhui Lin * 5bf72c9c9SXuhui Lin */ 6bf72c9c9SXuhui Lin 7bf72c9c9SXuhui Lin #ifndef __CONFIG_RK3576_COMMON_H 8bf72c9c9SXuhui Lin #define __CONFIG_RK3576_COMMON_H 9bf72c9c9SXuhui Lin 10*4ee44385SBinyuan Lan #define CFG_CPUID_OFFSET 0xa 11*4ee44385SBinyuan Lan 12bf72c9c9SXuhui Lin #include "rockchip-common.h" 13bf72c9c9SXuhui Lin 14bf72c9c9SXuhui Lin #define CONFIG_SPL_FRAMEWORK 15bf72c9c9SXuhui Lin #define CONFIG_SPL_TEXT_BASE 0x40000000 16bf72c9c9SXuhui Lin #define CONFIG_SPL_MAX_SIZE 0x00040000 17bf72c9c9SXuhui Lin #define CONFIG_SPL_BSS_START_ADDR 0x43fe0000 18bf72c9c9SXuhui Lin #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 19bf72c9c9SXuhui Lin #define CONFIG_SPL_STACK 0x43fe0000 20bf72c9c9SXuhui Lin #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 21bf72c9c9SXuhui Lin #undef CONFIG_SPL_LOAD_FIT_ADDRESS 22bf72c9c9SXuhui Lin #endif 23bf72c9c9SXuhui Lin #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x42000000 24bf72c9c9SXuhui Lin 25bf72c9c9SXuhui Lin #define CONFIG_SYS_MALLOC_LEN (32 << 20) 26bf72c9c9SXuhui Lin #define CONFIG_SYS_CBSIZE 1024 27bf72c9c9SXuhui Lin 28bf72c9c9SXuhui Lin #ifdef CONFIG_SUPPORT_USBPLUG 29682a1dd9SXuhui Lin #define CONFIG_SYS_TEXT_BASE 0x40000000 30bf72c9c9SXuhui Lin #else 31bf72c9c9SXuhui Lin #define CONFIG_SYS_TEXT_BASE 0x40200000 32bf72c9c9SXuhui Lin #endif 33bf72c9c9SXuhui Lin 34bf72c9c9SXuhui Lin #define CONFIG_SYS_INIT_SP_ADDR 0x40400000 35682a1dd9SXuhui Lin #define CONFIG_SYS_LOAD_ADDR 0x40700800 36bf72c9c9SXuhui Lin #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 37bf72c9c9SXuhui Lin #define COUNTER_FREQUENCY 24000000 38bf72c9c9SXuhui Lin 39682a1dd9SXuhui Lin #define GICD_BASE 0x2a701000 40682a1dd9SXuhui Lin #define GICC_BASE 0x2a702000 41682a1dd9SXuhui Lin 421a31aec1SXuhui Lin /* secure otp */ 431a31aec1SXuhui Lin #define OTP_UBOOT_ROLLBACK_OFFSET 0x610 441a31aec1SXuhui Lin #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 451a31aec1SXuhui Lin #define OTP_ALL_ONES_NUM_BITS 32 461a31aec1SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 471a31aec1SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_SIZE 1 481a31aec1SXuhui Lin #define OTP_RSA4096_ENABLE_ADDR 0x21 491a31aec1SXuhui Lin #define OTP_RSA4096_ENABLE_SIZE 1 501a31aec1SXuhui Lin #define OTP_RSA_HASH_ADDR 0x200 511a31aec1SXuhui Lin #define OTP_RSA_HASH_SIZE 32 521a31aec1SXuhui Lin 53bf72c9c9SXuhui Lin #define CONFIG_BOUNCE_BUFFER 54bf72c9c9SXuhui Lin #define CONFIG_SYS_SDRAM_BASE 0x40000000 55bf72c9c9SXuhui Lin #define SDRAM_MAX_SIZE (0x100000000 - CONFIG_SYS_SDRAM_BASE) /* max 4G */ 56bf72c9c9SXuhui Lin #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1M */ 57bf72c9c9SXuhui Lin 58bf72c9c9SXuhui Lin /* env used only in U-Boot */ 59bf72c9c9SXuhui Lin #ifndef CONFIG_SPL_BUILD 60bf72c9c9SXuhui Lin /* usb mass storage */ 61bf72c9c9SXuhui Lin #define CONFIG_USB_FUNCTION_MASS_STORAGE 62bf72c9c9SXuhui Lin #define CONFIG_ROCKUSB_G_DNL_PID 0x350e 63bf72c9c9SXuhui Lin 64bf72c9c9SXuhui Lin /* 65682a1dd9SXuhui Lin * DDR layout mainly follow rk3588 Soc 66bf72c9c9SXuhui Lin */ 67bf72c9c9SXuhui Lin #define ENV_MEM_LAYOUT_SETTINGS \ 68bf72c9c9SXuhui Lin "scriptaddr=0x40500000\0" \ 69bf72c9c9SXuhui Lin "pxefile_addr_r=0x40600000\0" \ 70682a1dd9SXuhui Lin "fdt_addr_r=0x48300000\0" \ 71682a1dd9SXuhui Lin "kernel_addr_r=0x40400000\0" \ 72682a1dd9SXuhui Lin "kernel_addr_c=0x45480000\0" \ 73682a1dd9SXuhui Lin "ramdisk_addr_r=0x4a200000\0" 74682a1dd9SXuhui Lin 75bf72c9c9SXuhui Lin #include <config_distro_bootcmd.h> 76bf72c9c9SXuhui Lin 77bf72c9c9SXuhui Lin #define CONFIG_EXTRA_ENV_SETTINGS \ 78bf72c9c9SXuhui Lin ENV_MEM_LAYOUT_SETTINGS \ 79bf72c9c9SXuhui Lin "partitions=" PARTS_RKIMG \ 80bf72c9c9SXuhui Lin ROCKCHIP_DEVICE_SETTINGS \ 81bf72c9c9SXuhui Lin RKIMG_DET_BOOTDEV \ 82bf72c9c9SXuhui Lin BOOTENV 83bf72c9c9SXuhui Lin #endif /* !CONFIG_SPL_BUILD */ 84bf72c9c9SXuhui Lin 85bf72c9c9SXuhui Lin /* rockchip ohci host driver */ 86bf72c9c9SXuhui Lin #define CONFIG_USB_OHCI_NEW 87bf72c9c9SXuhui Lin #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 88bf72c9c9SXuhui Lin 89bf72c9c9SXuhui Lin #define CONFIG_PREBOOT 90bf72c9c9SXuhui Lin #define CONFIG_LIB_HW_RAND 91bf72c9c9SXuhui Lin 92bf72c9c9SXuhui Lin #endif /* __CONFIG_RK3576_COMMON_H */ 93