185e5c210SXuhui Lin /* SPDX-License-Identifier: GPL-2.0+ */ 285e5c210SXuhui Lin /* 385e5c210SXuhui Lin * (C) Copyright 2024 Rockchip Electronics Co., Ltd 485e5c210SXuhui Lin * 585e5c210SXuhui Lin */ 685e5c210SXuhui Lin 785e5c210SXuhui Lin #ifndef __CONFIG_RK3506_COMMON_H 885e5c210SXuhui Lin #define __CONFIG_RK3506_COMMON_H 985e5c210SXuhui Lin 1085e5c210SXuhui Lin #include "rockchip-common.h" 1185e5c210SXuhui Lin 1285e5c210SXuhui Lin #define COUNTER_FREQUENCY 24000000 1385e5c210SXuhui Lin #define CONFIG_SYS_MALLOC_LEN (16 << 20) 1485e5c210SXuhui Lin #define CONFIG_SYS_CBSIZE 1024 1585e5c210SXuhui Lin #define CONFIG_SYS_TEXT_BASE 0x00200000 16*53bf6228SXuhui Lin #define CONFIG_SYS_INIT_SP_ADDR 0x00600000 1785e5c210SXuhui Lin #define CONFIG_SYS_LOAD_ADDR 0x00008000 1885e5c210SXuhui Lin #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 1985e5c210SXuhui Lin #define CONFIG_SYS_SDRAM_BASE 0 2085e5c210SXuhui Lin #define SDRAM_MAX_SIZE 0xc0000000 2185e5c210SXuhui Lin #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 2285e5c210SXuhui Lin 2385e5c210SXuhui Lin /* SPL */ 2485e5c210SXuhui Lin #define CONFIG_SPL_FRAMEWORK 25a106936cSJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x03f00000 2685e5c210SXuhui Lin #define CONFIG_SPL_MAX_SIZE 0x40000 27a106936cSJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 2885e5c210SXuhui Lin #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 29c293c786SXuhui Lin #define CONFIG_SPL_STACK 0x03f00000 3085e5c210SXuhui Lin 3185e5c210SXuhui Lin #define GICD_BASE 0xff581000 3285e5c210SXuhui Lin #define GICC_BASE 0xff582000 3385e5c210SXuhui Lin 34a106936cSJoseph Chen #define ATAGS_OFFSET 0x62000 35a106936cSJoseph Chen #define ATAGS_SIZE 0x01000 36a106936cSJoseph Chen 377ce57368SXuhui Lin /* secure otp */ 387ce57368SXuhui Lin #define OTP_UBOOT_ROLLBACK_OFFSET 0x350 397ce57368SXuhui Lin #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 407ce57368SXuhui Lin #define OTP_ALL_ONES_NUM_BITS 32 417ce57368SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 427ce57368SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_SIZE 1 437ce57368SXuhui Lin #define OTP_RSA_HASH_ADDR 0x180 447ce57368SXuhui Lin #define OTP_RSA_HASH_SIZE 32 457ce57368SXuhui Lin 4685e5c210SXuhui Lin /* MMC/SD IP block */ 4785e5c210SXuhui Lin #define CONFIG_BOUNCE_BUFFER 4885e5c210SXuhui Lin 4985e5c210SXuhui Lin #ifndef CONFIG_SPL_BUILD 5085e5c210SXuhui Lin /* usb mass storage */ 5185e5c210SXuhui Lin #define CONFIG_USB_FUNCTION_MASS_STORAGE 5285e5c210SXuhui Lin #define CONFIG_ROCKUSB_G_DNL_PID 0x350f 5385e5c210SXuhui Lin 5485e5c210SXuhui Lin #define CONFIG_LIB_HW_RAND 5585e5c210SXuhui Lin #define CONFIG_PREBOOT 5685e5c210SXuhui Lin 5785e5c210SXuhui Lin /* 58a106936cSJoseph Chen * fdt: 396K - 524K 59a106936cSJoseph Chen * Image: 1M+32k - 16M 60a106936cSJoseph Chen * zImage: 16M - 24M 61a106936cSJoseph Chen * ramdisk: 24M - ... 6285e5c210SXuhui Lin */ 6385e5c210SXuhui Lin #define ENV_MEM_LAYOUT_SETTINGS \ 6485e5c210SXuhui Lin "scriptaddr=0x00b00000\0" \ 6585e5c210SXuhui Lin "pxefile_addr_r=0x00c00000\0" \ 66a106936cSJoseph Chen "fdt_addr_r=0x00063000\0" \ 6765daedb1SXuhui Lin "kernel_addr_r=0x00108000\0" \ 68a106936cSJoseph Chen "kernel_addr_c=0x01100000\0" \ 69a106936cSJoseph Chen "ramdisk_addr_r=0x01800000\0" 7085e5c210SXuhui Lin 7185e5c210SXuhui Lin #include <config_distro_bootcmd.h> 7285e5c210SXuhui Lin 7385e5c210SXuhui Lin #define CONFIG_EXTRA_ENV_SETTINGS \ 7485e5c210SXuhui Lin ENV_MEM_LAYOUT_SETTINGS \ 7585e5c210SXuhui Lin "partitions=" PARTS_RKIMG \ 7685e5c210SXuhui Lin ROCKCHIP_DEVICE_SETTINGS \ 7785e5c210SXuhui Lin RKIMG_DET_BOOTDEV \ 7885e5c210SXuhui Lin BOOTENV 7985e5c210SXuhui Lin 8085e5c210SXuhui Lin #undef RKIMG_BOOTCOMMAND 8185e5c210SXuhui Lin #ifdef CONFIG_FIT_SIGNATURE 8285e5c210SXuhui Lin #define RKIMG_BOOTCOMMAND \ 8385e5c210SXuhui Lin "boot_fit;" 8485e5c210SXuhui Lin #else 8585e5c210SXuhui Lin #define RKIMG_BOOTCOMMAND \ 8685e5c210SXuhui Lin "boot_fit;" \ 8785e5c210SXuhui Lin "boot_android ${devtype} ${devnum};" 8885e5c210SXuhui Lin #endif 8985e5c210SXuhui Lin 9085e5c210SXuhui Lin #endif 9185e5c210SXuhui Lin #endif 92