1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3188_COMMON_H 8 #define __CONFIG_RK3188_COMMON_H 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #include <asm/arch/hardware.h> 13 #include "rockchip-common.h" 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 16 #define CONFIG_SYS_NO_FLASH 17 #define CONFIG_NR_DRAM_BANKS 1 18 #define CONFIG_ENV_SIZE 0x2000 19 #define CONFIG_SYS_MAXARGS 16 20 #define CONFIG_BAUDRATE 115200 21 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 22 #define CONFIG_SYS_CBSIZE 1024 23 #define CONFIG_SYS_THUMB_BUILD 24 25 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 26 #define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ 27 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 28 #define CONFIG_SYS_TIMER_COUNTS_DOWN 29 30 #define CONFIG_SYS_NS16550_MEM32 31 #define CONFIG_SPL_BOARD_INIT 32 33 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 34 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ 35 #define CONFIG_SYS_TEXT_BASE 0x60000000 36 #else 37 #define CONFIG_SYS_TEXT_BASE 0x60100000 38 #endif 39 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 40 #define CONFIG_SYS_LOAD_ADDR 0x60800800 41 42 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) 43 #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" 44 45 #ifdef CONFIG_TPL_BUILD 46 #define CONFIG_SPL_TEXT_BASE 0x10080804 47 /* tpl size 1kb - 4byte RK31 header */ 48 #define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) 49 #elif defined(CONFIG_SPL_BUILD) 50 /* spl size 32kb sram - 2kb bootrom - 1kb spl */ 51 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) 52 #define CONFIG_SPL_TEXT_BASE 0x10080C00 53 #define CONFIG_SPL_FRAMEWORK 1 54 #define CONFIG_SPL_CLK 1 55 #define CONFIG_SPL_PINCTRL 1 56 #define CONFIG_SPL_REGMAP 1 57 #define CONFIG_SPL_SYSCON 1 58 #define CONFIG_SPL_RAM 1 59 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 60 #define CONFIG_ROCKCHIP_SERIAL 1 61 #endif 62 63 #define CONFIG_SPL_STACK 0x10087fff 64 65 /* MMC/SD IP block */ 66 #define CONFIG_BOUNCE_BUFFER 67 68 #define CONFIG_FAT_WRITE 69 70 #define CONFIG_SYS_SDRAM_BASE 0x60000000 71 #define CONFIG_NR_DRAM_BANKS 1 72 #define SDRAM_BANK_SIZE (2UL << 30) 73 74 #define CONFIG_SPI_FLASH 75 #define CONFIG_SPI 76 #define CONFIG_SF_DEFAULT_SPEED 20000000 77 78 #ifndef CONFIG_SPL_BUILD 79 /* usb otg */ 80 #define CONFIG_USB_GADGET 81 #define CONFIG_USB_GADGET_DUALSPEED 82 #define CONFIG_USB_GADGET_DWC2_OTG 83 #define CONFIG_ROCKCHIP_USB2_PHY 84 #define CONFIG_USB_GADGET_VBUS_DRAW 0 85 86 #define CONFIG_USB_GADGET_DOWNLOAD 87 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 88 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 89 #define CONFIG_G_DNL_PRODUCT_NUM 0x310a 90 91 /* usb host support */ 92 #ifdef CONFIG_CMD_USB 93 #define CONFIG_USB_DWC2 94 #define CONFIG_USB_HOST_ETHER 95 #define CONFIG_USB_ETHER_SMSC95XX 96 #define CONFIG_USB_ETHER_ASIX 97 #endif 98 #define ENV_MEM_LAYOUT_SETTINGS \ 99 "scriptaddr=0x60000000\0" \ 100 "pxefile_addr_r=0x60100000\0" \ 101 "fdt_addr_r=0x61f00000\0" \ 102 "kernel_addr_r=0x62000000\0" \ 103 "ramdisk_addr_r=0x64000000\0" 104 105 #include <config_distro_bootcmd.h> 106 107 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board, 108 * so limit the fdt reallocation to that */ 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "fdt_high=0x6fffffff\0" \ 111 "initrd_high=0x6fffffff\0" \ 112 "partitions=" PARTS_DEFAULT \ 113 ENV_MEM_LAYOUT_SETTINGS \ 114 ROCKCHIP_DEVICE_SETTINGS \ 115 BOOTENV 116 117 #endif /* CONFIG_SPL_BUILD */ 118 119 #define CONFIG_PREBOOT 120 121 #endif 122