1*578306eaSPaweł Jarosz /* 2*578306eaSPaweł Jarosz * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com> 3*578306eaSPaweł Jarosz * 4*578306eaSPaweł Jarosz * SPDX-License-Identifier: GPL-2.0+ 5*578306eaSPaweł Jarosz */ 6*578306eaSPaweł Jarosz 7*578306eaSPaweł Jarosz #ifndef __CONFIG_RK3066_COMMON_H 8*578306eaSPaweł Jarosz #define __CONFIG_RK3066_COMMON_H 9*578306eaSPaweł Jarosz 10*578306eaSPaweł Jarosz #include <asm/arch/hardware.h> 11*578306eaSPaweł Jarosz #include "rockchip-common.h" 12*578306eaSPaweł Jarosz 13*578306eaSPaweł Jarosz #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 14*578306eaSPaweł Jarosz #define CONFIG_SYS_MAXARGS 16 15*578306eaSPaweł Jarosz #define CONFIG_BAUDRATE 115200 16*578306eaSPaweł Jarosz #define CONFIG_SYS_MALLOC_LEN (64 << 20) 17*578306eaSPaweł Jarosz #define CONFIG_SYS_CBSIZE 256 18*578306eaSPaweł Jarosz 19*578306eaSPaweł Jarosz #define CONFIG_SYS_SDRAM_BASE 0x60000000 20*578306eaSPaweł Jarosz #define CONFIG_NR_DRAM_BANKS 1 21*578306eaSPaweł Jarosz #define SDRAM_BANK_SIZE (1024UL << 20UL) 22*578306eaSPaweł Jarosz #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE 23*578306eaSPaweł Jarosz 24*578306eaSPaweł Jarosz #define CONFIG_SYS_TIMER_RATE 24000000 25*578306eaSPaweł Jarosz #define CONFIG_SYS_TIMER_BASE 0x20038000 26*578306eaSPaweł Jarosz #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4) 27*578306eaSPaweł Jarosz #define CONFIG_SYS_TIMER_COUNTS_DOWN 28*578306eaSPaweł Jarosz 29*578306eaSPaweł Jarosz #define CONFIG_SYS_TEXT_BASE 0x60408000 30*578306eaSPaweł Jarosz #define CONFIG_SYS_INIT_SP_ADDR 0x78000000 31*578306eaSPaweł Jarosz #define CONFIG_SYS_LOAD_ADDR 0x70800800 32*578306eaSPaweł Jarosz 33*578306eaSPaweł Jarosz #define CONFIG_SYS_NS16550_MEM32 34*578306eaSPaweł Jarosz #define CONFIG_BOUNCE_BUFFER 35*578306eaSPaweł Jarosz #define CONFIG_SPL_FRAMEWORK 36*578306eaSPaweł Jarosz 37*578306eaSPaweł Jarosz #define CONFIG_SYS_MAX_NAND_DEVICE 8 38*578306eaSPaweł Jarosz 39*578306eaSPaweł Jarosz #ifdef CONFIG_TPL_BUILD 40*578306eaSPaweł Jarosz #define CONFIG_SPL_TEXT_BASE 0x10080C04 41*578306eaSPaweł Jarosz #define CONFIG_SPL_STACK 0x1008FFFF 42*578306eaSPaweł Jarosz /* tpl size max 32kb - 4byte RK30 header */ 43*578306eaSPaweł Jarosz #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4) 44*578306eaSPaweł Jarosz #elif defined(CONFIG_SPL_BUILD) 45*578306eaSPaweł Jarosz /* spl size max 200k */ 46*578306eaSPaweł Jarosz #define CONFIG_SPL_MAX_SIZE 0x32000 47*578306eaSPaweł Jarosz #define CONFIG_SPL_TEXT_BASE 0x60000000 48*578306eaSPaweł Jarosz #define CONFIG_SPL_STACK 0x1008FFFF 49*578306eaSPaweł Jarosz #define CONFIG_SPL_BOARD_INIT 50*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_DRIVERS 51*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_LOAD 52*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_ECC 53*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_BASE 54*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_INIT 55*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_BBT 56*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_IDS 57*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_UTIL 58*578306eaSPaweł Jarosz #define CONFIG_SPL_NAND_RAW_ONLY 59*578306eaSPaweł Jarosz #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 60*578306eaSPaweł Jarosz #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 61*578306eaSPaweł Jarosz #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 62*578306eaSPaweł Jarosz #define CONFIG_EXTRA_ENV_SETTINGS ROCKCHIP_DEVICE_SETTINGS 63*578306eaSPaweł Jarosz #define CONFIG_MTD_DEVICE 64*578306eaSPaweł Jarosz #endif 65*578306eaSPaweł Jarosz 66*578306eaSPaweł Jarosz #include <config_distro_defaults.h> 67*578306eaSPaweł Jarosz 68*578306eaSPaweł Jarosz #ifndef CONFIG_SPL_BUILD 69*578306eaSPaweł Jarosz 70*578306eaSPaweł Jarosz #define CONFIG_USB_FUNCTION_MASS_STORAGE 71*578306eaSPaweł Jarosz 72*578306eaSPaweł Jarosz #define CONFIG_MTD_DEVICE 73*578306eaSPaweł Jarosz #define MTDIDS_DEFAULT "nand0=rockchip-nand.0" 74*578306eaSPaweł Jarosz 75*578306eaSPaweł Jarosz #define ENV_MEM_LAYOUT_SETTINGS \ 76*578306eaSPaweł Jarosz "scriptaddr=0x60000000\0" \ 77*578306eaSPaweł Jarosz "pxefile_addr_r=0x60100000\0" \ 78*578306eaSPaweł Jarosz "fdt_addr_r=0x61f00000\0" \ 79*578306eaSPaweł Jarosz "kernel_addr_r=0x62000000\0" \ 80*578306eaSPaweł Jarosz "ramdisk_addr_r=0x64000000\0" 81*578306eaSPaweł Jarosz 82*578306eaSPaweł Jarosz #include <config_distro_bootcmd.h> 83*578306eaSPaweł Jarosz 84*578306eaSPaweł Jarosz #define CONFIG_EXTRA_ENV_SETTINGS \ 85*578306eaSPaweł Jarosz "fdt_high=0x6fffffff\0" \ 86*578306eaSPaweł Jarosz "initrd_high=0x6fffffff\0" \ 87*578306eaSPaweł Jarosz "partitions=" PARTS_DEFAULT \ 88*578306eaSPaweł Jarosz "mtdids=" MTDIDS_DEFAULT "\0" \ 89*578306eaSPaweł Jarosz ENV_MEM_LAYOUT_SETTINGS \ 90*578306eaSPaweł Jarosz ROCKCHIP_DEVICE_SETTINGS \ 91*578306eaSPaweł Jarosz BOOTENV 92*578306eaSPaweł Jarosz 93*578306eaSPaweł Jarosz #endif 94*578306eaSPaweł Jarosz 95*578306eaSPaweł Jarosz #define CONFIG_PREBOOT 96*578306eaSPaweł Jarosz 97*578306eaSPaweł Jarosz #endif 98