1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK1808_COMMON_H 8 #define __CONFIG_RK1808_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 #define CONFIG_SYS_TEXT_BASE 0x00600000 16 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 17 #define CONFIG_SYS_LOAD_ADDR 0x00800800 18 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 19 #define COUNTER_FREQUENCY 24000000 20 21 #define GICD_BASE 0xff100000 22 #define GICR_BASE 0xff140000 23 #define GICC_BASE 0xff300000 24 25 /* MMC/SD IP block */ 26 #define CONFIG_BOUNCE_BUFFER 27 #define CONFIG_SUPPORT_EMMC_RPMB 28 29 #define CONFIG_SYS_SDRAM_BASE 0 30 #define SDRAM_MAX_SIZE 0xf8000000 31 #define SDRAM_BANK_SIZE (2UL << 30) 32 #define CONFIG_PREBOOT 33 34 #ifndef CONFIG_SPL_BUILD 35 /* usb mass storage */ 36 #define CONFIG_USB_FUNCTION_MASS_STORAGE 37 #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 38 39 #define ENV_MEM_LAYOUT_SETTINGS \ 40 "scriptaddr=0x00500000\0" \ 41 "pxefile_addr_r=0x00600000\0" \ 42 "fdt_addr_r=0x01f00000\0" \ 43 "kernel_addr_no_bl32_r=0x00280000\0" \ 44 "kernel_addr_r=0x00680000\0" \ 45 "kernel_addr_c=0x04080000\0" \ 46 "ramdisk_addr_r=0x0a200000\0" 47 48 #include <config_distro_bootcmd.h> 49 50 #ifdef CONFIG_DM_RAMDISK 51 #undef RKIMG_DET_BOOTDEV 52 #define RKIMG_DET_BOOTDEV \ 53 "rkimg_bootdev=" \ 54 "setenv devtype ramdisk; setenv devnum 0; \0" 55 #endif 56 57 #define CONFIG_EXTRA_ENV_SETTINGS \ 58 ENV_MEM_LAYOUT_SETTINGS \ 59 "partitions=" PARTS_DEFAULT \ 60 ROCKCHIP_DEVICE_SETTINGS \ 61 RKIMG_DET_BOOTDEV \ 62 BOOTENV 63 #endif 64 65 #endif /* __CONFIG_RK1808_COMMON_H */ 66