1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #ifndef __CONFIG_RK1808_COMMON_H 8 #define __CONFIG_RK1808_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 #define CONFIG_SYS_TEXT_BASE 0x00600000 16 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 17 #define CONFIG_SYS_LOAD_ADDR 0x00800800 18 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 19 #define COUNTER_FREQUENCY 24000000 20 21 #define GICD_BASE 0xff100000 22 #define GICR_BASE 0xff140000 23 #define GICC_BASE 0xff300000 24 25 /* MMC/SD IP block */ 26 #define CONFIG_BOUNCE_BUFFER 27 28 #define CONFIG_SYS_SDRAM_BASE 0 29 #define SDRAM_MAX_SIZE 0xf8000000 30 #define SDRAM_BANK_SIZE (2UL << 30) 31 #define CONFIG_PREBOOT 32 33 #ifndef CONFIG_SPL_BUILD 34 /* usb mass storage */ 35 #define CONFIG_USB_FUNCTION_MASS_STORAGE 36 #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 37 38 #define ENV_MEM_LAYOUT_SETTINGS \ 39 "scriptaddr=0x00500000\0" \ 40 "pxefile_addr_r=0x00600000\0" \ 41 "fdt_addr_r=0x01f00000\0" \ 42 "kernel_addr_no_bl32_r=0x00280000\0" \ 43 "kernel_addr_r=0x00680000\0" \ 44 "kernel_addr_c=0x04080000\0" \ 45 "ramdisk_addr_r=0x0a200000\0" 46 47 #include <config_distro_bootcmd.h> 48 49 #ifdef CONFIG_DM_RAMDISK 50 #undef RKIMG_DET_BOOTDEV 51 #define RKIMG_DET_BOOTDEV \ 52 "rkimg_bootdev=" \ 53 "setenv devtype ramdisk; setenv devnum 0; \0" 54 #endif 55 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 ENV_MEM_LAYOUT_SETTINGS \ 58 "partitions=" PARTS_DEFAULT \ 59 ROCKCHIP_DEVICE_SETTINGS \ 60 RKIMG_DET_BOOTDEV \ 61 BOOTENV 62 #endif 63 64 #endif /* __CONFIG_RK1808_COMMON_H */ 65