1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #undef DEBUG 5 6 #define CONFIG_SH4 1 7 #define CONFIG_CPU_SH7751 1 8 #define CONFIG_CPU_SH_TYPE_R 1 9 #define CONFIG_R2DPLUS 1 10 #define __LITTLE_ENDIAN__ 1 11 12 /* 13 * Command line configuration. 14 */ 15 #include <config_cmd_default.h> 16 17 #define CONFIG_CMD_CACHE 18 #define CONFIG_CMD_FLASH 19 #define CONFIG_CMD_PCI 20 #define CONFIG_CMD_NET 21 #define CONFIG_CMD_PING 22 #define CONFIG_CMD_IDE 23 #define CONFIG_CMD_EXT2 24 #define CONFIG_DOS_PARTITION 25 #define CONFIG_CMD_SH_ZIMAGEBOOT 26 27 /* SCIF */ 28 #define CONFIG_SCIF_CONSOLE 1 29 #define CONFIG_BAUDRATE 115200 30 #define CONFIG_CONS_SCIF1 1 31 #define CONFIG_BOARD_LATE_INIT 32 33 #define CONFIG_BOOTDELAY -1 34 #define CONFIG_BOOTARGS "console=ttySC0,115200" 35 #define CONFIG_ENV_OVERWRITE 1 36 37 /* SDRAM */ 38 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 39 #define CONFIG_SYS_SDRAM_SIZE (0x04000000) 40 41 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 42 #define CONFIG_SYS_LONGHELP 43 #define CONFIG_SYS_CBSIZE 256 44 #define CONFIG_SYS_PBSIZE 256 45 #define CONFIG_SYS_MAXARGS 16 46 #define CONFIG_SYS_BARGSIZE 512 47 48 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 49 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 50 51 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 52 /* Address of u-boot image in Flash */ 53 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 54 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 55 /* Size of DRAM reserved for malloc() use */ 56 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 57 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 58 59 /* 60 * NOR Flash ( Spantion S29GL256P ) 61 */ 62 #define CONFIG_SYS_FLASH_CFI 63 #define CONFIG_FLASH_CFI_DRIVER 64 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 65 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 66 #define CONFIG_SYS_MAX_FLASH_SECT 256 67 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 68 69 #define CONFIG_ENV_IS_IN_FLASH 70 #define CONFIG_ENV_SECT_SIZE 0x40000 71 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 72 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 73 74 /* 75 * SuperH Clock setting 76 */ 77 #define CONFIG_SYS_CLK_FREQ 60000000 78 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 80 #define CONFIG_SYS_TMU_CLK_DIV 4 81 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 82 83 /* 84 * IDE support 85 */ 86 #define CONFIG_IDE_RESET 1 87 #define CONFIG_SYS_PIO_MODE 1 88 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 89 #define CONFIG_SYS_IDE_MAXDEVICE 1 90 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 91 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 92 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 93 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 94 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 95 #define CONFIG_IDE_SWAP_IO 96 97 /* 98 * SuperH PCI Bridge Configration 99 */ 100 #define CONFIG_PCI 101 #define CONFIG_SH4_PCI 102 #define CONFIG_SH7751_PCI 103 #define CONFIG_PCI_PNP 104 #define CONFIG_PCI_SCAN_SHOW 1 105 #define __io 106 #define __mem_pci 107 108 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 109 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 110 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 111 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 112 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 113 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 114 #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 115 #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 116 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 117 118 /* 119 * Network device (RTL8139) support 120 */ 121 #define CONFIG_RTL8139 122 123 #endif /* __CONFIG_H */ 124