xref: /rk3399_rockchip-uboot/include/configs/porter.h (revision 3146f0c017df2231d03dff09cee31f7bd63db3e5)
1 /*
2  * include/configs/porter.h
3  *     This file is Porter board configuration.
4  *
5  * Copyright (C) 2015 Renesas Electronics Corporation
6  * Copyright (C) 2015 Cogent Embedded, Inc.
7  *
8  * SPDX-License-Identifier: GPL-2.0
9  */
10 
11 #ifndef __PORTER_H
12 #define __PORTER_H
13 
14 #undef DEBUG
15 #define CONFIG_R8A7791
16 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
17 
18 #include "rcar-gen2-common.h"
19 
20 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
21 #define CONFIG_SYS_TEXT_BASE	0x70000000
22 #else
23 #define CONFIG_SYS_TEXT_BASE	0xE6304000
24 #endif
25 
26 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
27 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
28 #else
29 #define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
30 #endif
31 #define STACK_AREA_SIZE			0xC000
32 #define LOW_LEVEL_MERAM_STACK \
33 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34 
35 /* MEMORY */
36 #define RCAR_GEN2_SDRAM_BASE		0x40000000
37 #define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE	(1024u * 1024 * 1024)
39 
40 /* SCIF */
41 
42 /* FLASH */
43 #define CONFIG_SPI
44 #define CONFIG_SH_QSPI
45 #define CONFIG_SPI_FLASH_QUAD
46 
47 /* SH Ether */
48 #define CONFIG_SH_ETHER
49 #define CONFIG_SH_ETHER_USE_PORT	0
50 #define CONFIG_SH_ETHER_PHY_ADDR	0x1
51 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
52 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
53 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
54 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
55 #define CONFIG_PHY_MICREL
56 #define CONFIG_BITBANGMII
57 #define CONFIG_BITBANGMII_MULTI
58 
59 /* Board Clock */
60 #define RMOBILE_XTAL_CLK	20000000u
61 #define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
62 #define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
63 #define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
64 #define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)
65 
66 #define CONFIG_SYS_TMU_CLK_DIV	4
67 
68 /* i2c */
69 #define CONFIG_SYS_I2C
70 #define CONFIG_SYS_I2C_SH
71 #define CONFIG_SYS_I2C_SLAVE		0x7F
72 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
73 #define CONFIG_SYS_I2C_SH_SPEED0	400000
74 #define CONFIG_SYS_I2C_SH_SPEED1	400000
75 #define CONFIG_SYS_I2C_SH_SPEED2	400000
76 #define CONFIG_SH_I2C_DATA_HIGH		4
77 #define CONFIG_SH_I2C_DATA_LOW		5
78 #define CONFIG_SH_I2C_CLOCK		10000000
79 
80 #define CONFIG_SYS_I2C_POWERIC_ADDR	0x58 /* da9063 */
81 
82 /* USB */
83 #define CONFIG_USB_EHCI_RMOBILE
84 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
85 
86 /* SD */
87 #define CONFIG_SH_SDHI_FREQ	97500000
88 
89 /* Module stop status bits */
90 /* INTC-RT */
91 #define CONFIG_SMSTP0_ENA	0x00400000
92 /* MSIF */
93 #define CONFIG_SMSTP2_ENA	0x00002000
94 /* INTC-SYS, IRQC */
95 #define CONFIG_SMSTP4_ENA	0x00000180
96 /* SCIF0 */
97 #define CONFIG_SMSTP7_ENA	0x00200000
98 
99 #endif /* __PORTER_H */
100