1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* ARM asynchronous clock */ 32 #define CONFIG_DISPLAY_CPUINFO 33 #define CONFIG_DISPLAY_BOARDINFO 34 35 #define MASTER_PLL_DIV 15 36 #define MASTER_PLL_MUL 162 37 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 38 #define AT91_MAIN_CLOCK 18432000 39 40 #define CONFIG_SYS_HZ 1000 41 42 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 43 #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ 44 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 45 #define CONFIG_ARCH_CPU_INIT 46 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 47 48 /* clocks */ 49 #define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ 50 #define CONFIG_SYS_PLLAR_VAL \ 51 (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 52 53 #if (MAIN_PLL_DIV == 2) 54 /* PCK/2 = MCK Master Clock from PLLA */ 55 #define CONFIG_SYS_MCKR1_VAL 0x00000100 56 /* PCK/2 = MCK Master Clock from PLLA */ 57 #define CONFIG_SYS_MCKR2_VAL 0x00000102 58 #else 59 /* PCK/4 = MCK Master Clock from PLLA */ 60 #define CONFIG_SYS_MCKR1_VAL 0x00000200 61 /* PCK/4 = MCK Master Clock from PLLA */ 62 #define CONFIG_SYS_MCKR2_VAL 0x00000202 63 #endif 64 /* define PDC[31:16] as DATA[31:16] */ 65 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 66 /* no pull-up for D[31:16] */ 67 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 68 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 69 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A 70 71 /* SDRAM */ 72 /* SDRAMC_MR Mode register */ 73 #define CONFIG_SYS_SDRC_MR_VAL1 0 74 /* SDRAMC_TR - Refresh Timer register */ 75 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 76 #define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/ 77 /* Memory Device Register -> SDRAM */ 78 #define CONFIG_SYS_SDRC_MDR_VAL 0 79 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ 80 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 81 #define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */ 82 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 83 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 84 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 85 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 86 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 87 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 88 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 89 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 90 #define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */ 91 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 92 #define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */ 93 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 94 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 95 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 96 97 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 98 #define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ 99 #define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ 100 #define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ 101 #define CONFIG_SYS_SMC0_MODE0_VAL 0x00161003 /* SMC_MODE */ 102 103 #define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ 104 105 /* Watchdog */ 106 #define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ 107 108 /* */ 109 110 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 111 #define CONFIG_SETUP_MEMORY_TAGS 1 112 #define CONFIG_INITRD_TAG 1 113 114 #undef CONFIG_SKIP_LOWLEVEL_INIT 115 #undef CONFIG_SKIP_RELOCATE_UBOOT 116 #define CONFIG_USER_LOWLEVEL_INIT 1 117 118 /* 119 * Hardware drivers 120 */ 121 #define CONFIG_ATMEL_USART 1 122 #undef CONFIG_USART0 123 #undef CONFIG_USART1 124 #undef CONFIG_USART2 125 #define CONFIG_USART3 1 /* USART 3 is DBGU */ 126 127 /* LCD */ 128 #define CONFIG_LCD 1 129 #define LCD_BPP LCD_COLOR8 130 #define CONFIG_LCD_LOGO 1 131 #undef LCD_TEST_PATTERN 132 #define CONFIG_LCD_INFO 1 133 #define CONFIG_LCD_INFO_BELOW_LOGO 1 134 #define CONFIG_SYS_WHITE_ON_BLACK 1 135 #define CONFIG_ATMEL_LCD 1 136 #define CONFIG_ATMEL_LCD_BGR555 1 137 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 138 139 #define CONFIG_LCD_IN_PSRAM 1 140 141 /* LED */ 142 #define CONFIG_AT91_LED 143 #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ 144 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ 145 146 #define CONFIG_BOOTDELAY 3 147 148 /* 149 * BOOTP options 150 */ 151 #define CONFIG_BOOTP_BOOTFILESIZE 1 152 #define CONFIG_BOOTP_BOOTPATH 1 153 #define CONFIG_BOOTP_GATEWAY 1 154 #define CONFIG_BOOTP_HOSTNAME 1 155 156 /* 157 * Command line configuration. 158 */ 159 #include <config_cmd_default.h> 160 #undef CONFIG_CMD_BDI 161 #undef CONFIG_CMD_IMI 162 #undef CONFIG_CMD_AUTOSCRIPT 163 #undef CONFIG_CMD_FPGA 164 #undef CONFIG_CMD_LOADS 165 #undef CONFIG_CMD_IMLS 166 167 #define CONFIG_CMD_PING 1 168 #define CONFIG_CMD_DHCP 1 169 #define CONFIG_CMD_NAND 1 170 #define CONFIG_CMD_USB 1 171 172 /* SDRAM */ 173 #define CONFIG_NR_DRAM_BANKS 1 174 #define PHYS_SDRAM 0x20000000 175 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 176 177 /* DataFlash */ 178 #define CONFIG_ATMEL_DATAFLASH_SPI 179 #define CONFIG_HAS_DATAFLASH 1 180 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 181 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 182 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 183 #define AT91_SPI_CLK 15000000 184 #define DATAFLASH_TCSS (0x1a << 16) 185 #define DATAFLASH_TCHS (0x1 << 24) 186 187 /* NOR flash, if populated */ 188 #define CONFIG_SYS_FLASH_CFI 1 189 #define CONFIG_FLASH_CFI_DRIVER 1 190 #define PHYS_FLASH_1 0x10000000 191 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 192 #define CONFIG_SYS_MAX_FLASH_SECT 256 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 194 195 /* NAND flash */ 196 #ifdef CONFIG_CMD_NAND 197 #define CONFIG_NAND_ATMEL 198 #define CONFIG_SYS_NAND_MAX_CHIPS 1 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_SYS_NAND_BASE 0x40000000 201 #define CONFIG_SYS_NAND_DBW_8 1 202 /* our ALE is AD21 */ 203 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 204 /* our CLE is AD22 */ 205 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 206 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 207 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30 208 #endif 209 210 #define CONFIG_CMD_JFFS2 1 211 #define CONFIG_JFFS2_CMDLINE 1 212 #define CONFIG_JFFS2_NAND 1 213 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 214 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 215 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 216 217 /* PSRAM */ 218 #define PHYS_PSRAM 0x70000000 219 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 220 221 /* Ethernet */ 222 #define CONFIG_MACB 1 223 #define CONFIG_RMII 1 224 #define CONFIG_NET_MULTI 1 225 #define CONFIG_NET_RETRY_COUNT 20 226 #define CONFIG_RESET_PHY_R 1 227 228 /* USB */ 229 #define CONFIG_USB_ATMEL 230 #define CONFIG_USB_OHCI_NEW 1 231 #define CONFIG_DOS_PARTITION 1 232 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 233 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 234 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 235 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 236 #define CONFIG_USB_STORAGE 1 237 238 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 239 240 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 241 #define CONFIG_SYS_MEMTEST_END 0x23e00000 242 243 #define CONFIG_SYS_USE_FLASH 1 244 #undef CONFIG_SYS_USE_DATAFLASH 245 #undef CONFIG_SYS_USE_NANDFLASH 246 247 #ifdef CONFIG_SYS_USE_DATAFLASH 248 249 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 250 #define CONFIG_ENV_IS_IN_DATAFLASH 251 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 252 #define CONFIG_ENV_OFFSET 0x4200 253 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 254 #define CONFIG_ENV_SIZE 0x4200 255 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 256 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 257 "root=/dev/mtdblock0 " \ 258 "mtdparts=at91_nand:-(root) "\ 259 "rw rootfstype=jffs2" 260 261 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 262 263 /* bootstrap + u-boot + env + linux in nandflash */ 264 #define CONFIG_ENV_IS_IN_NAND 265 #define CONFIG_ENV_OFFSET 0x60000 266 #define CONFIG_ENV_OFFSET_REDUND 0x80000 267 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 268 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 269 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 270 "root=/dev/mtdblock5 " \ 271 "mtdparts=at91_nand:" \ 272 "128k(bootstrap)ro," \ 273 "256k(uboot)ro," \ 274 "128k(env1)ro," \ 275 "128k(env2)ro," \ 276 "2M(linux)," \ 277 "-(root) " \ 278 "rw rootfstype=jffs2" 279 280 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 281 282 #define CONFIG_ENV_IS_IN_FLASH 1 283 #define CONFIG_ENV_OFFSET 0x40000 284 #define CONFIG_ENV_SECT_SIZE 0x10000 285 #define CONFIG_ENV_SIZE 0x10000 286 #define CONFIG_ENV_OVERWRITE 1 287 288 /* JFFS Partition offset set */ 289 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 290 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 291 292 /* 512k reserved for u-boot */ 293 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 294 295 #define CONFIG_BOOTCOMMAND "run flashboot" 296 #define CONFIG_ROOTPATH /ronetix/rootfs 297 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" 298 299 #define CONFIG_CON_ROT "fbcon=rotate:3 " 300 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 301 CONFIG_CON_ROT 302 303 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 304 #define MTDPARTS_DEFAULT \ 305 "mtdparts=physmap-flash.0:" \ 306 "256k(u-boot)ro," \ 307 "64k(u-boot-env)ro," \ 308 "1408k(kernel)," \ 309 "-(rootfs);" \ 310 "nand:-(nand)" 311 312 #define CONFIG_EXTRA_ENV_SETTINGS \ 313 "mtdids=" MTDIDS_DEFAULT "\0" \ 314 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 315 "partition=nand0,0\0" \ 316 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 317 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 318 CONFIG_CON_ROT \ 319 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 320 "addip=setenv bootargs $(bootargs) " \ 321 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 322 ":$(hostname):eth0:off\0" \ 323 "ramboot=tftpboot 0x22000000 vmImage;" \ 324 "run ramargs;run addip;bootm 22000000\0" \ 325 "nfsboot=tftpboot 0x22000000 vmImage;" \ 326 "run nfsargs;run addip;bootm 22000000\0" \ 327 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 328 "" 329 330 #else 331 #error "Undefined memory device" 332 #endif 333 334 #define CONFIG_BAUDRATE 115200 335 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 336 337 #define CONFIG_SYS_PROMPT "u-boot-pm9263> " 338 #define CONFIG_SYS_CBSIZE 256 339 #define CONFIG_SYS_MAXARGS 16 340 #define CONFIG_SYS_PBSIZE \ 341 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 342 #define CONFIG_SYS_LONGHELP 1 343 #define CONFIG_CMDLINE_EDITING 1 344 345 #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) 346 /* 347 * Size of malloc() pool 348 */ 349 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 350 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ 351 352 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ 353 354 #ifdef CONFIG_USE_IRQ 355 #error CONFIG_USE_IRQ not supported 356 #endif 357 358 #endif 359