1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 /* ARM asynchronous clock */ 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define MASTER_PLL_DIV 6 25 #define MASTER_PLL_MUL 65 26 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 29 30 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 31 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 32 #define CONFIG_ARCH_CPU_INIT 33 #define CONFIG_SYS_TEXT_BASE 0 34 35 #define MACH_TYPE_PM9263 1475 36 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 37 38 /* clocks */ 39 #define CONFIG_SYS_MOR_VAL \ 40 (AT91_PMC_MOR_MOSCEN | \ 41 (255 << 8)) /* Main Oscillator Start-up Time */ 42 #define CONFIG_SYS_PLLAR_VAL \ 43 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 44 AT91_PMC_PLLXR_OUT(3) | \ 45 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 46 (2 << 28) | /* PLL Clock Frequency Range */ \ 47 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 48 49 #if (MAIN_PLL_DIV == 2) 50 /* PCK/2 = MCK Master Clock from PLLA */ 51 #define CONFIG_SYS_MCKR1_VAL \ 52 (AT91_PMC_MCKR_CSS_SLOW | \ 53 AT91_PMC_MCKR_PRES_1 | \ 54 AT91_PMC_MCKR_MDIV_2) 55 /* PCK/2 = MCK Master Clock from PLLA */ 56 #define CONFIG_SYS_MCKR2_VAL \ 57 (AT91_PMC_MCKR_CSS_PLLA | \ 58 AT91_PMC_MCKR_PRES_1 | \ 59 AT91_PMC_MCKR_MDIV_2) 60 #else 61 /* PCK/4 = MCK Master Clock from PLLA */ 62 #define CONFIG_SYS_MCKR1_VAL \ 63 (AT91_PMC_MCKR_CSS_SLOW | \ 64 AT91_PMC_MCKR_PRES_1 | \ 65 AT91_PMC_MCKR_MDIV_4) 66 /* PCK/4 = MCK Master Clock from PLLA */ 67 #define CONFIG_SYS_MCKR2_VAL \ 68 (AT91_PMC_MCKR_CSS_PLLA | \ 69 AT91_PMC_MCKR_PRES_1 | \ 70 AT91_PMC_MCKR_MDIV_4) 71 #endif 72 /* define PDC[31:16] as DATA[31:16] */ 73 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 74 /* no pull-up for D[31:16] */ 75 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 76 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 77 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 78 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 79 AT91_MATRIX_CSA_EBI_CS1A) 80 81 /* SDRAM */ 82 /* SDRAMC_MR Mode register */ 83 #define CONFIG_SYS_SDRC_MR_VAL1 0 84 /* SDRAMC_TR - Refresh Timer register */ 85 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 86 /* SDRAMC_CR - Configuration register*/ 87 #define CONFIG_SYS_SDRC_CR_VAL \ 88 (AT91_SDRAMC_NC_9 | \ 89 AT91_SDRAMC_NR_13 | \ 90 AT91_SDRAMC_NB_4 | \ 91 AT91_SDRAMC_CAS_2 | \ 92 AT91_SDRAMC_DBW_32 | \ 93 (2 << 8) | /* tWR - Write Recovery Delay */ \ 94 (7 << 12) | /* tRC - Row Cycle Delay */ \ 95 (2 << 16) | /* tRP - Row Precharge Delay */ \ 96 (2 << 20) | /* tRCD - Row to Column Delay */ \ 97 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 98 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 99 100 /* Memory Device Register -> SDRAM */ 101 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 102 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 103 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 104 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 105 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 106 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 108 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 113 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 114 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 115 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 116 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 117 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 118 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 119 120 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 121 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 122 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 123 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 124 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 125 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 126 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 127 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 128 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 129 #define CONFIG_SYS_SMC0_MODE0_VAL \ 130 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 131 AT91_SMC_MODE_DBW_16 | \ 132 AT91_SMC_MODE_TDF | \ 133 AT91_SMC_MODE_TDF_CYCLE(6)) 134 135 /* user reset enable */ 136 #define CONFIG_SYS_RSTC_RMR_VAL \ 137 (AT91_RSTC_KEY | \ 138 AT91_RSTC_CR_PROCRST | \ 139 AT91_RSTC_MR_ERSTL(1) | \ 140 AT91_RSTC_MR_ERSTL(2)) 141 142 /* Disable Watchdog */ 143 #define CONFIG_SYS_WDTC_WDMR_VAL \ 144 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 145 AT91_WDT_MR_WDV(0xfff) | \ 146 AT91_WDT_MR_WDDIS | \ 147 AT91_WDT_MR_WDD(0xfff)) 148 149 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 150 #define CONFIG_SETUP_MEMORY_TAGS 1 151 #define CONFIG_INITRD_TAG 1 152 153 #undef CONFIG_SKIP_LOWLEVEL_INIT 154 #define CONFIG_USER_LOWLEVEL_INIT 1 155 #define CONFIG_BOARD_EARLY_INIT_F 156 157 /* 158 * Hardware drivers 159 */ 160 #define CONFIG_AT91_GPIO 1 161 #define CONFIG_ATMEL_USART 1 162 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 163 #define CONFIG_USART_ID ATMEL_ID_SYS 164 165 /* LCD */ 166 #define CONFIG_LCD 1 167 #define LCD_BPP LCD_COLOR8 168 #define CONFIG_LCD_LOGO 1 169 #undef LCD_TEST_PATTERN 170 #define CONFIG_LCD_INFO 1 171 #define CONFIG_LCD_INFO_BELOW_LOGO 1 172 #define CONFIG_SYS_WHITE_ON_BLACK 1 173 #define CONFIG_ATMEL_LCD 1 174 #define CONFIG_ATMEL_LCD_BGR555 1 175 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 176 177 #define CONFIG_LCD_IN_PSRAM 1 178 179 /* LED */ 180 #define CONFIG_AT91_LED 181 #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ 182 #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ 183 184 185 /* 186 * BOOTP options 187 */ 188 #define CONFIG_BOOTP_BOOTFILESIZE 1 189 #define CONFIG_BOOTP_BOOTPATH 1 190 #define CONFIG_BOOTP_GATEWAY 1 191 #define CONFIG_BOOTP_HOSTNAME 1 192 193 /* 194 * Command line configuration. 195 */ 196 #define CONFIG_CMD_NAND 1 197 198 /* SDRAM */ 199 #define CONFIG_NR_DRAM_BANKS 1 200 #define PHYS_SDRAM 0x20000000 201 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 202 203 /* DataFlash */ 204 #define CONFIG_ATMEL_DATAFLASH_SPI 205 #define CONFIG_HAS_DATAFLASH 1 206 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 207 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 208 #define AT91_SPI_CLK 15000000 209 #define DATAFLASH_TCSS (0x1a << 16) 210 #define DATAFLASH_TCHS (0x1 << 24) 211 212 /* NOR flash, if populated */ 213 #define CONFIG_SYS_FLASH_CFI 1 214 #define CONFIG_FLASH_CFI_DRIVER 1 215 #define PHYS_FLASH_1 0x10000000 216 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 217 #define CONFIG_SYS_MAX_FLASH_SECT 256 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 219 220 /* NAND flash */ 221 #ifdef CONFIG_CMD_NAND 222 #define CONFIG_NAND_ATMEL 223 #define CONFIG_SYS_MAX_NAND_DEVICE 1 224 #define CONFIG_SYS_NAND_BASE 0x40000000 225 #define CONFIG_SYS_NAND_DBW_8 1 226 /* our ALE is AD21 */ 227 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 228 /* our CLE is AD22 */ 229 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 230 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 231 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 232 233 #endif 234 235 #define CONFIG_CMD_JFFS2 1 236 #define CONFIG_JFFS2_CMDLINE 1 237 #define CONFIG_JFFS2_NAND 1 238 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 239 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 240 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 241 242 /* PSRAM */ 243 #define PHYS_PSRAM 0x70000000 244 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 245 /* Slave EBI1, PSRAM connected */ 246 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 247 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 248 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 249 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 250 251 /* Ethernet */ 252 #define CONFIG_MACB 1 253 #define CONFIG_RMII 1 254 #define CONFIG_NET_RETRY_COUNT 20 255 #define CONFIG_RESET_PHY_R 1 256 257 /* USB */ 258 #define CONFIG_USB_ATMEL 259 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 260 #define CONFIG_USB_OHCI_NEW 1 261 #define CONFIG_DOS_PARTITION 1 262 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 263 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 264 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 265 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 266 267 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 268 269 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 270 #define CONFIG_SYS_MEMTEST_END 0x23e00000 271 272 #define CONFIG_SYS_USE_FLASH 1 273 #undef CONFIG_SYS_USE_DATAFLASH 274 #undef CONFIG_SYS_USE_NANDFLASH 275 276 #ifdef CONFIG_SYS_USE_DATAFLASH 277 278 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 279 #define CONFIG_ENV_IS_IN_DATAFLASH 280 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 281 #define CONFIG_ENV_OFFSET 0x4200 282 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 283 #define CONFIG_ENV_SIZE 0x4200 284 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 285 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 286 "root=/dev/mtdblock0 " \ 287 "mtdparts=atmel_nand:-(root) "\ 288 "rw rootfstype=jffs2" 289 290 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 291 292 /* bootstrap + u-boot + env + linux in nandflash */ 293 #define CONFIG_ENV_IS_IN_NAND 294 #define CONFIG_ENV_OFFSET 0x60000 295 #define CONFIG_ENV_OFFSET_REDUND 0x80000 296 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 297 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 298 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 299 "root=/dev/mtdblock5 " \ 300 "mtdparts=atmel_nand:" \ 301 "128k(bootstrap)ro," \ 302 "256k(uboot)ro," \ 303 "128k(env1)ro," \ 304 "128k(env2)ro," \ 305 "2M(linux)," \ 306 "-(root) " \ 307 "rw rootfstype=jffs2" 308 309 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 310 311 #define CONFIG_ENV_IS_IN_FLASH 1 312 #define CONFIG_ENV_OFFSET 0x40000 313 #define CONFIG_ENV_SECT_SIZE 0x10000 314 #define CONFIG_ENV_SIZE 0x10000 315 #define CONFIG_ENV_OVERWRITE 1 316 317 /* JFFS Partition offset set */ 318 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 319 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 320 321 /* 512k reserved for u-boot */ 322 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 323 324 #define CONFIG_BOOTCOMMAND "run flashboot" 325 #define CONFIG_ROOTPATH "/ronetix/rootfs" 326 327 #define CONFIG_CON_ROT "fbcon=rotate:3 " 328 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 329 CONFIG_CON_ROT 330 331 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 332 #define MTDPARTS_DEFAULT \ 333 "mtdparts=physmap-flash.0:" \ 334 "256k(u-boot)ro," \ 335 "64k(u-boot-env)ro," \ 336 "1408k(kernel)," \ 337 "-(rootfs);" \ 338 "nand:-(nand)" 339 340 #define CONFIG_EXTRA_ENV_SETTINGS \ 341 "mtdids=" MTDIDS_DEFAULT "\0" \ 342 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 343 "partition=nand0,0\0" \ 344 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 345 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 346 CONFIG_CON_ROT \ 347 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 348 "addip=setenv bootargs $(bootargs) " \ 349 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 350 ":$(hostname):eth0:off\0" \ 351 "ramboot=tftpboot 0x22000000 vmImage;" \ 352 "run ramargs;run addip;bootm 22000000\0" \ 353 "nfsboot=tftpboot 0x22000000 vmImage;" \ 354 "run nfsargs;run addip;bootm 22000000\0" \ 355 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 356 "" 357 358 #else 359 #error "Undefined memory device" 360 #endif 361 362 #define CONFIG_BAUDRATE 115200 363 364 #define CONFIG_SYS_CBSIZE 256 365 #define CONFIG_SYS_MAXARGS 16 366 #define CONFIG_SYS_PBSIZE \ 367 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 368 #define CONFIG_SYS_LONGHELP 1 369 #define CONFIG_CMDLINE_EDITING 1 370 371 /* 372 * Size of malloc() pool 373 */ 374 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 375 376 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 377 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 378 GENERATED_GBL_DATA_SIZE) 379 380 #endif 381