1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9261 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 20 #include <asm/hardware.h> 21 /* ARM asynchronous clock */ 22 23 #define MASTER_PLL_DIV 15 24 #define MASTER_PLL_MUL 162 25 #define MAIN_PLL_DIV 2 26 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 28 29 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" 30 #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ 31 #define CONFIG_ARCH_CPU_INIT 32 #define CONFIG_SYS_TEXT_BASE 0 33 34 #define MACH_TYPE_PM9261 1187 35 #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 36 37 /* clocks */ 38 /* CKGR_MOR - enable main osc. */ 39 #define CONFIG_SYS_MOR_VAL \ 40 (AT91_PMC_MOR_MOSCEN | \ 41 (255 << 8)) /* Main Oscillator Start-up Time */ 42 #define CONFIG_SYS_PLLAR_VAL \ 43 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 44 AT91_PMC_PLLXR_OUT(3) | \ 45 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 46 47 /* PCK/2 = MCK Master Clock from PLLA */ 48 #define CONFIG_SYS_MCKR1_VAL \ 49 (AT91_PMC_MCKR_CSS_SLOW | \ 50 AT91_PMC_MCKR_PRES_1 | \ 51 AT91_PMC_MCKR_MDIV_2) 52 53 /* PCK/2 = MCK Master Clock from PLLA */ 54 #define CONFIG_SYS_MCKR2_VAL \ 55 (AT91_PMC_MCKR_CSS_PLLA | \ 56 AT91_PMC_MCKR_PRES_1 | \ 57 AT91_PMC_MCKR_MDIV_2) 58 59 /* define PDC[31:16] as DATA[31:16] */ 60 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 61 /* no pull-up for D[31:16] */ 62 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 63 64 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ 65 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 66 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) 67 68 /* SDRAM */ 69 /* SDRAMC_MR Mode register */ 70 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL 71 /* SDRAMC_TR - Refresh Timer register */ 72 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 73 /* SDRAMC_CR - Configuration register*/ 74 #define CONFIG_SYS_SDRC_CR_VAL \ 75 (AT91_SDRAMC_NC_9 | \ 76 AT91_SDRAMC_NR_13 | \ 77 AT91_SDRAMC_NB_4 | \ 78 AT91_SDRAMC_CAS_3 | \ 79 AT91_SDRAMC_DBW_32 | \ 80 (1 << 8) | /* Write Recovery Delay */ \ 81 (7 << 12) | /* Row Cycle Delay */ \ 82 (3 << 16) | /* Row Precharge Delay */ \ 83 (2 << 20) | /* Row to Column Delay */ \ 84 (5 << 24) | /* Active to Precharge Delay */ \ 85 (1 << 28)) /* Exit Self Refresh to Active Delay */ 86 87 /* Memory Device Register -> SDRAM */ 88 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 89 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 90 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 91 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 92 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 93 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 94 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 95 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 96 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 97 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 98 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 99 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 100 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 101 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 102 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 103 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 104 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 105 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 106 107 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 108 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 109 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 110 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 111 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 112 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 113 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 114 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 115 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 116 #define CONFIG_SYS_SMC0_MODE0_VAL \ 117 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 118 AT91_SMC_MODE_DBW_16 | \ 119 AT91_SMC_MODE_TDF | \ 120 AT91_SMC_MODE_TDF_CYCLE(6)) 121 122 /* user reset enable */ 123 #define CONFIG_SYS_RSTC_RMR_VAL \ 124 (AT91_RSTC_KEY | \ 125 AT91_RSTC_CR_PROCRST | \ 126 AT91_RSTC_MR_ERSTL(1) | \ 127 AT91_RSTC_MR_ERSTL(2)) 128 129 /* Disable Watchdog */ 130 #define CONFIG_SYS_WDTC_WDMR_VAL \ 131 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 132 AT91_WDT_MR_WDV(0xfff) | \ 133 AT91_WDT_MR_WDDIS | \ 134 AT91_WDT_MR_WDD(0xfff)) 135 136 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 137 #define CONFIG_SETUP_MEMORY_TAGS 1 138 #define CONFIG_INITRD_TAG 1 139 140 #undef CONFIG_SKIP_LOWLEVEL_INIT 141 #define CONFIG_BOARD_EARLY_INIT_F 142 143 /* 144 * Hardware drivers 145 */ 146 #define CONFIG_AT91_GPIO 1 147 #define CONFIG_ATMEL_USART 1 148 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 149 #define CONFIG_USART_ID ATMEL_ID_SYS 150 151 /* LCD */ 152 #define LCD_BPP LCD_COLOR8 153 #define CONFIG_LCD_LOGO 1 154 #undef LCD_TEST_PATTERN 155 #define CONFIG_LCD_INFO 1 156 #define CONFIG_LCD_INFO_BELOW_LOGO 1 157 #define CONFIG_SYS_WHITE_ON_BLACK 1 158 #define CONFIG_ATMEL_LCD 1 159 #define CONFIG_ATMEL_LCD_BGR555 1 160 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 161 162 /* LED */ 163 #define CONFIG_AT91_LED 164 #define CONFIG_RED_LED GPIO_PIN_PC(12) 165 #define CONFIG_GREEN_LED GPIO_PIN_PC(13) 166 #define CONFIG_YELLOW_LED GPIO_PIN_PC(15) 167 168 169 /* 170 * BOOTP options 171 */ 172 #define CONFIG_BOOTP_BOOTFILESIZE 1 173 #define CONFIG_BOOTP_BOOTPATH 1 174 #define CONFIG_BOOTP_GATEWAY 1 175 #define CONFIG_BOOTP_HOSTNAME 1 176 177 /* 178 * Command line configuration. 179 */ 180 #define CONFIG_CMD_NAND 1 181 182 /* SDRAM */ 183 #define CONFIG_NR_DRAM_BANKS 1 184 #define PHYS_SDRAM 0x20000000 185 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 186 187 /* DataFlash */ 188 #define CONFIG_ATMEL_DATAFLASH_SPI 189 #define CONFIG_HAS_DATAFLASH 190 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 191 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 192 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ 193 #define AT91_SPI_CLK 15000000 194 #define DATAFLASH_TCSS (0x1a << 16) 195 #define DATAFLASH_TCHS (0x1 << 24) 196 197 /* NAND flash */ 198 #define CONFIG_NAND_ATMEL 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_SYS_NAND_BASE 0x40000000 201 #define CONFIG_SYS_NAND_DBW_8 1 202 /* our ALE is AD22 */ 203 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) 204 /* our CLE is AD21 */ 205 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) 206 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 207 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) 208 209 /* NOR flash */ 210 #define CONFIG_SYS_FLASH_CFI 1 211 #define CONFIG_FLASH_CFI_DRIVER 1 212 #define PHYS_FLASH_1 0x10000000 213 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 214 #define CONFIG_SYS_MAX_FLASH_SECT 256 215 #define CONFIG_SYS_MAX_FLASH_BANKS 1 216 217 /* Ethernet */ 218 #define CONFIG_DRIVER_DM9000 1 219 #define CONFIG_DM9000_BASE 0x30000000 220 #define DM9000_IO CONFIG_DM9000_BASE 221 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 222 #define CONFIG_DM9000_USE_16BIT 1 223 #define CONFIG_NET_RETRY_COUNT 20 224 #define CONFIG_RESET_PHY_R 1 225 226 /* USB */ 227 #define CONFIG_USB_ATMEL 228 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 229 #define CONFIG_USB_OHCI_NEW 1 230 #define CONFIG_DOS_PARTITION 1 231 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 232 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 233 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" 234 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 235 236 #define CONFIG_SYS_LOAD_ADDR 0x22000000 237 238 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 239 #define CONFIG_SYS_MEMTEST_END 0x23e00000 240 241 #undef CONFIG_SYS_USE_DATAFLASH_CS0 242 #undef CONFIG_SYS_USE_NANDFLASH 243 #define CONFIG_SYS_USE_FLASH 1 244 245 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 246 247 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 248 #define CONFIG_ENV_IS_IN_DATAFLASH 1 249 #define CONFIG_SYS_MONITOR_BASE \ 250 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 251 #define CONFIG_ENV_OFFSET 0x4200 252 #define CONFIG_ENV_ADDR \ 253 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 254 #define CONFIG_ENV_SIZE 0x4200 255 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 256 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 257 "root=/dev/mtdblock0 " \ 258 "mtdparts=atmel_nand:-(root) " \ 259 "rw rootfstype=jffs2" 260 261 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ 262 263 /* bootstrap + u-boot + env + linux in nandflash */ 264 #define CONFIG_ENV_IS_IN_NAND 1 265 #define CONFIG_ENV_OFFSET 0x60000 266 #define CONFIG_ENV_OFFSET_REDUND 0x80000 267 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 268 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 269 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 270 "root=/dev/mtdblock5 " \ 271 "mtdparts=atmel_nand:128k(bootstrap)ro," \ 272 "256k(uboot)ro,128k(env1)ro," \ 273 "128k(env2)ro,2M(linux),-(root) " \ 274 "rw rootfstype=jffs2" 275 276 #elif defined (CONFIG_SYS_USE_FLASH) 277 278 #define CONFIG_ENV_IS_IN_FLASH 1 279 #define CONFIG_ENV_OFFSET 0x40000 280 #define CONFIG_ENV_SECT_SIZE 0x10000 281 #define CONFIG_ENV_SIZE 0x10000 282 #define CONFIG_ENV_OVERWRITE 1 283 284 /* JFFS Partition offset set */ 285 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 286 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 287 288 /* 512k reserved for u-boot */ 289 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 290 291 #define CONFIG_BOOTCOMMAND "run flashboot" 292 293 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 294 #define MTDPARTS_DEFAULT \ 295 "mtdparts=physmap-flash.0:" \ 296 "256k(u-boot)ro," \ 297 "64k(u-boot-env)ro," \ 298 "1408k(kernel)," \ 299 "-(rootfs);" \ 300 "nand:-(nand)" 301 302 #define CONFIG_CON_ROT "fbcon=rotate:3 " 303 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT 304 305 #define CONFIG_EXTRA_ENV_SETTINGS \ 306 "mtdids=" MTDIDS_DEFAULT "\0" \ 307 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 308 "partition=nand0,0\0" \ 309 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 310 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 311 CONFIG_CON_ROT \ 312 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 313 "addip=setenv bootargs $(bootargs) " \ 314 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 315 ":$(hostname):eth0:off\0" \ 316 "ramboot=tftpboot 0x22000000 vmImage;" \ 317 "run ramargs;run addip;bootm 22000000\0" \ 318 "nfsboot=tftpboot 0x22000000 vmImage;" \ 319 "run nfsargs;run addip;bootm 22000000\0" \ 320 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 321 "" 322 #else 323 #error "Undefined memory device" 324 #endif 325 326 #define CONFIG_BAUDRATE 115200 327 328 #define CONFIG_SYS_CBSIZE 256 329 #define CONFIG_SYS_MAXARGS 16 330 #define CONFIG_SYS_PBSIZE \ 331 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 332 #define CONFIG_SYS_LONGHELP 1 333 #define CONFIG_CMDLINE_EDITING 1 334 335 /* 336 * Size of malloc() pool 337 */ 338 #define CONFIG_SYS_MALLOC_LEN \ 339 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 340 341 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 342 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 343 GENERATED_GBL_DATA_SIZE) 344 345 #endif 346