xref: /rk3399_rockchip-uboot/include/configs/platinum_titanium.h (revision 6e7adf7037c76f081b149685fa5e978e2ddf2a22)
1*5d6050fdSStefan Roese /*
2*5d6050fdSStefan Roese  * Copyright (C) 2014, Barco (www.barco.com)
3*5d6050fdSStefan Roese  *
4*5d6050fdSStefan Roese  * SPDX-License-Identifier:	GPL-2.0+
5*5d6050fdSStefan Roese  */
6*5d6050fdSStefan Roese 
7*5d6050fdSStefan Roese #ifndef __PLATINUM_TITANIUM_CONFIG_H__
8*5d6050fdSStefan Roese #define __PLATINUM_TITANIUM_CONFIG_H__
9*5d6050fdSStefan Roese 
10*5d6050fdSStefan Roese #define CONFIG_PLATINUM_TITANIUM
11*5d6050fdSStefan Roese #define CONFIG_PLATINUM_BOARD			"Barco Titanium"
12*5d6050fdSStefan Roese #define CONFIG_PLATINUM_PROJECT			"titanium"
13*5d6050fdSStefan Roese #define CONFIG_PLATINUM_CPU			"imx6q"
14*5d6050fdSStefan Roese 
15*5d6050fdSStefan Roese #define PHYS_SDRAM_SIZE				(512 << 20)
16*5d6050fdSStefan Roese #define CONFIG_SYS_NAND_MAX_CHIPS		1
17*5d6050fdSStefan Roese 
18*5d6050fdSStefan Roese #include <configs/platinum.h>
19*5d6050fdSStefan Roese 
20*5d6050fdSStefan Roese #define CONFIG_FEC_XCV_TYPE			RGMII
21*5d6050fdSStefan Roese #define CONFIG_FEC_MXC_PHYADDR			4
22*5d6050fdSStefan Roese 
23*5d6050fdSStefan Roese #define CONFIG_PHY_RESET_DELAY			1000
24*5d6050fdSStefan Roese 
25*5d6050fdSStefan Roese #define CONFIG_HOSTNAME				titanium
26*5d6050fdSStefan Roese 
27*5d6050fdSStefan Roese #define CONFIG_PLATFORM_ENV_SETTINGS		"\0"
28*5d6050fdSStefan Roese 
29*5d6050fdSStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_COMMON_ENV_SETTINGS \
30*5d6050fdSStefan Roese 						CONFIG_PLATFORM_ENV_SETTINGS
31*5d6050fdSStefan Roese 
32*5d6050fdSStefan Roese #endif /* __PLATINUM_TITANIUM_CONFIG_H__ */
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