xref: /rk3399_rockchip-uboot/include/configs/pico-imx7d.h (revision 1541d7a63d46309651bb6cb8abee018c04b7dfa2)
1*1541d7a6SVanessa Maegima /*
2*1541d7a6SVanessa Maegima  * Copyright (C) 2017 NXP Semiconductors
3*1541d7a6SVanessa Maegima  *
4*1541d7a6SVanessa Maegima  * Configuration settings for the i.MX7D Pico board.
5*1541d7a6SVanessa Maegima  *
6*1541d7a6SVanessa Maegima  * SPDX-License-Identifier:    GPL-2.0+
7*1541d7a6SVanessa Maegima  */
8*1541d7a6SVanessa Maegima 
9*1541d7a6SVanessa Maegima #ifndef __PICO_IMX7D_CONFIG_H
10*1541d7a6SVanessa Maegima #define __PICO_IMX7D_CONFIG_H
11*1541d7a6SVanessa Maegima 
12*1541d7a6SVanessa Maegima #include "mx7_common.h"
13*1541d7a6SVanessa Maegima 
14*1541d7a6SVanessa Maegima #define PHYS_SDRAM_SIZE		SZ_1G
15*1541d7a6SVanessa Maegima 
16*1541d7a6SVanessa Maegima /* Size of malloc() pool */
17*1541d7a6SVanessa Maegima #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
18*1541d7a6SVanessa Maegima 
19*1541d7a6SVanessa Maegima #define CONFIG_MXC_UART_BASE		UART5_IPS_BASE_ADDR
20*1541d7a6SVanessa Maegima 
21*1541d7a6SVanessa Maegima /* Network */
22*1541d7a6SVanessa Maegima #define CONFIG_FEC_MXC
23*1541d7a6SVanessa Maegima #define CONFIG_MII
24*1541d7a6SVanessa Maegima #define CONFIG_FEC_XCV_TYPE		RGMII
25*1541d7a6SVanessa Maegima #define CONFIG_ETHPRIME			"FEC"
26*1541d7a6SVanessa Maegima #define CONFIG_FEC_MXC_PHYADDR		1
27*1541d7a6SVanessa Maegima 
28*1541d7a6SVanessa Maegima #define CONFIG_PHYLIB
29*1541d7a6SVanessa Maegima #define CONFIG_PHY_ATHEROS
30*1541d7a6SVanessa Maegima 
31*1541d7a6SVanessa Maegima /* ENET1 */
32*1541d7a6SVanessa Maegima #define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
33*1541d7a6SVanessa Maegima 
34*1541d7a6SVanessa Maegima /* MMC Config */
35*1541d7a6SVanessa Maegima #define CONFIG_SYS_FSL_ESDHC_ADDR	0
36*1541d7a6SVanessa Maegima 
37*1541d7a6SVanessa Maegima #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
38*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
39*1541d7a6SVanessa Maegima 
40*1541d7a6SVanessa Maegima #define CONFIG_EXTRA_ENV_SETTINGS \
41*1541d7a6SVanessa Maegima 	"script=boot.scr\0" \
42*1541d7a6SVanessa Maegima 	"image=zImage\0" \
43*1541d7a6SVanessa Maegima 	"console=ttymxc4\0" \
44*1541d7a6SVanessa Maegima 	"fdt_high=0xffffffff\0" \
45*1541d7a6SVanessa Maegima 	"initrd_high=0xffffffff\0" \
46*1541d7a6SVanessa Maegima 	"fdt_file=imx7d-pico.dtb\0" \
47*1541d7a6SVanessa Maegima 	"fdt_addr=0x83000000\0" \
48*1541d7a6SVanessa Maegima 	"ip_dyn=yes\0" \
49*1541d7a6SVanessa Maegima 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
50*1541d7a6SVanessa Maegima 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
51*1541d7a6SVanessa Maegima 	"finduuid=part uuid mmc 0:2 uuid\0" \
52*1541d7a6SVanessa Maegima 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
53*1541d7a6SVanessa Maegima 		"root=PARTUUID=${uuid} rootwait rw\0" \
54*1541d7a6SVanessa Maegima 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
55*1541d7a6SVanessa Maegima 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
56*1541d7a6SVanessa Maegima 	"mmcboot=echo Booting from mmc ...; " \
57*1541d7a6SVanessa Maegima 		"run finduuid; " \
58*1541d7a6SVanessa Maegima 		"run mmcargs; " \
59*1541d7a6SVanessa Maegima 		"if run loadfdt; then " \
60*1541d7a6SVanessa Maegima 			"bootz ${loadaddr} - ${fdt_addr}; " \
61*1541d7a6SVanessa Maegima 		"else " \
62*1541d7a6SVanessa Maegima 			"echo WARN: Cannot load the DT; " \
63*1541d7a6SVanessa Maegima 		"fi;\0" \
64*1541d7a6SVanessa Maegima 	"netargs=setenv bootargs console=${console},${baudrate} " \
65*1541d7a6SVanessa Maegima 		"root=/dev/nfs " \
66*1541d7a6SVanessa Maegima 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
67*1541d7a6SVanessa Maegima 		"netboot=echo Booting from net ...; " \
68*1541d7a6SVanessa Maegima 		"run netargs; " \
69*1541d7a6SVanessa Maegima 		"if test ${ip_dyn} = yes; then " \
70*1541d7a6SVanessa Maegima 			"setenv get_cmd dhcp; " \
71*1541d7a6SVanessa Maegima 		"else " \
72*1541d7a6SVanessa Maegima 			"setenv get_cmd tftp; " \
73*1541d7a6SVanessa Maegima 		"fi; " \
74*1541d7a6SVanessa Maegima 		"${get_cmd} ${image}; " \
75*1541d7a6SVanessa Maegima 		"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
76*1541d7a6SVanessa Maegima 			"bootz ${loadaddr} - ${fdt_addr}; " \
77*1541d7a6SVanessa Maegima 		"else " \
78*1541d7a6SVanessa Maegima 			"echo WARN: Cannot load the DT; " \
79*1541d7a6SVanessa Maegima 		"fi;\0"
80*1541d7a6SVanessa Maegima 
81*1541d7a6SVanessa Maegima #define CONFIG_BOOTCOMMAND \
82*1541d7a6SVanessa Maegima 	"if mmc rescan; then " \
83*1541d7a6SVanessa Maegima 		"if run loadimage; then " \
84*1541d7a6SVanessa Maegima 			"run mmcboot; " \
85*1541d7a6SVanessa Maegima 		"else run netboot; " \
86*1541d7a6SVanessa Maegima 		"fi; " \
87*1541d7a6SVanessa Maegima 	"else run netboot; fi"
88*1541d7a6SVanessa Maegima 
89*1541d7a6SVanessa Maegima #define CONFIG_SYS_MEMTEST_START	0x80000000
90*1541d7a6SVanessa Maegima #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
91*1541d7a6SVanessa Maegima 
92*1541d7a6SVanessa Maegima #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
93*1541d7a6SVanessa Maegima #define CONFIG_SYS_HZ			1000
94*1541d7a6SVanessa Maegima 
95*1541d7a6SVanessa Maegima /* Physical Memory Map */
96*1541d7a6SVanessa Maegima #define CONFIG_NR_DRAM_BANKS		1
97*1541d7a6SVanessa Maegima #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
98*1541d7a6SVanessa Maegima 
99*1541d7a6SVanessa Maegima #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
100*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
101*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
102*1541d7a6SVanessa Maegima 
103*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_SP_OFFSET \
104*1541d7a6SVanessa Maegima 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_SP_ADDR \
106*1541d7a6SVanessa Maegima 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
107*1541d7a6SVanessa Maegima 
108*1541d7a6SVanessa Maegima /* I2C configs */
109*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C
110*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC
111*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C1
112*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C2
113*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C3
114*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C4
115*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_SPEED		100000
116*1541d7a6SVanessa Maegima 
117*1541d7a6SVanessa Maegima /* PMIC */
118*1541d7a6SVanessa Maegima #define CONFIG_POWER
119*1541d7a6SVanessa Maegima #define CONFIG_POWER_I2C
120*1541d7a6SVanessa Maegima #define CONFIG_POWER_PFUZE3000
121*1541d7a6SVanessa Maegima #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
122*1541d7a6SVanessa Maegima 
123*1541d7a6SVanessa Maegima /* FLASH and environment organization */
124*1541d7a6SVanessa Maegima #define CONFIG_ENV_SIZE			SZ_8K
125*1541d7a6SVanessa Maegima #define CONFIG_ENV_IS_IN_MMC
126*1541d7a6SVanessa Maegima 
127*1541d7a6SVanessa Maegima #define CONFIG_ENV_OFFSET			(8 * SZ_64K)
128*1541d7a6SVanessa Maegima #define CONFIG_SYS_FSL_USDHC_NUM		2
129*1541d7a6SVanessa Maegima 
130*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_ENV_DEV			0
131*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_ENV_PART		0
132*1541d7a6SVanessa Maegima 
133*1541d7a6SVanessa Maegima /* USB Configs */
134*1541d7a6SVanessa Maegima #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
135*1541d7a6SVanessa Maegima #define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
136*1541d7a6SVanessa Maegima #define CONFIG_MXC_USB_FLAGS			0
137*1541d7a6SVanessa Maegima #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
138*1541d7a6SVanessa Maegima 
139*1541d7a6SVanessa Maegima #define CONFIG_IMX_THERMAL
140*1541d7a6SVanessa Maegima 
141*1541d7a6SVanessa Maegima #define CONFIG_USB_FUNCTION_MASS_STORAGE
142*1541d7a6SVanessa Maegima 
143*1541d7a6SVanessa Maegima #endif
144