1*1541d7a6SVanessa Maegima /* 2*1541d7a6SVanessa Maegima * Copyright (C) 2017 NXP Semiconductors 3*1541d7a6SVanessa Maegima * 4*1541d7a6SVanessa Maegima * Configuration settings for the i.MX7D Pico board. 5*1541d7a6SVanessa Maegima * 6*1541d7a6SVanessa Maegima * SPDX-License-Identifier: GPL-2.0+ 7*1541d7a6SVanessa Maegima */ 8*1541d7a6SVanessa Maegima 9*1541d7a6SVanessa Maegima #ifndef __PICO_IMX7D_CONFIG_H 10*1541d7a6SVanessa Maegima #define __PICO_IMX7D_CONFIG_H 11*1541d7a6SVanessa Maegima 12*1541d7a6SVanessa Maegima #include "mx7_common.h" 13*1541d7a6SVanessa Maegima 14*1541d7a6SVanessa Maegima #define PHYS_SDRAM_SIZE SZ_1G 15*1541d7a6SVanessa Maegima 16*1541d7a6SVanessa Maegima /* Size of malloc() pool */ 17*1541d7a6SVanessa Maegima #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) 18*1541d7a6SVanessa Maegima 19*1541d7a6SVanessa Maegima #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR 20*1541d7a6SVanessa Maegima 21*1541d7a6SVanessa Maegima /* Network */ 22*1541d7a6SVanessa Maegima #define CONFIG_FEC_MXC 23*1541d7a6SVanessa Maegima #define CONFIG_MII 24*1541d7a6SVanessa Maegima #define CONFIG_FEC_XCV_TYPE RGMII 25*1541d7a6SVanessa Maegima #define CONFIG_ETHPRIME "FEC" 26*1541d7a6SVanessa Maegima #define CONFIG_FEC_MXC_PHYADDR 1 27*1541d7a6SVanessa Maegima 28*1541d7a6SVanessa Maegima #define CONFIG_PHY_ATHEROS 29*1541d7a6SVanessa Maegima 30*1541d7a6SVanessa Maegima /* ENET1 */ 31*1541d7a6SVanessa Maegima #define IMX_FEC_BASE ENET_IPS_BASE_ADDR 32*1541d7a6SVanessa Maegima 33*1541d7a6SVanessa Maegima /* MMC Config */ 34*1541d7a6SVanessa Maegima #define CONFIG_SYS_FSL_ESDHC_ADDR 0 35*1541d7a6SVanessa Maegima 36*1541d7a6SVanessa Maegima #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 37*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 38*1541d7a6SVanessa Maegima 39*1541d7a6SVanessa Maegima #define CONFIG_EXTRA_ENV_SETTINGS \ 40*1541d7a6SVanessa Maegima "script=boot.scr\0" \ 41*1541d7a6SVanessa Maegima "image=zImage\0" \ 42*1541d7a6SVanessa Maegima "console=ttymxc4\0" \ 43*1541d7a6SVanessa Maegima "fdt_high=0xffffffff\0" \ 44*1541d7a6SVanessa Maegima "initrd_high=0xffffffff\0" \ 45*1541d7a6SVanessa Maegima "fdt_file=imx7d-pico.dtb\0" \ 46*1541d7a6SVanessa Maegima "fdt_addr=0x83000000\0" \ 47*1541d7a6SVanessa Maegima "ip_dyn=yes\0" \ 48*1541d7a6SVanessa Maegima "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 49*1541d7a6SVanessa Maegima "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 50*1541d7a6SVanessa Maegima "finduuid=part uuid mmc 0:2 uuid\0" \ 51*1541d7a6SVanessa Maegima "mmcargs=setenv bootargs console=${console},${baudrate} " \ 52*1541d7a6SVanessa Maegima "root=PARTUUID=${uuid} rootwait rw\0" \ 53*1541d7a6SVanessa Maegima "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 54*1541d7a6SVanessa Maegima "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 55*1541d7a6SVanessa Maegima "mmcboot=echo Booting from mmc ...; " \ 56*1541d7a6SVanessa Maegima "run finduuid; " \ 57*1541d7a6SVanessa Maegima "run mmcargs; " \ 58*1541d7a6SVanessa Maegima "if run loadfdt; then " \ 59*1541d7a6SVanessa Maegima "bootz ${loadaddr} - ${fdt_addr}; " \ 60*1541d7a6SVanessa Maegima "else " \ 61*1541d7a6SVanessa Maegima "echo WARN: Cannot load the DT; " \ 62*1541d7a6SVanessa Maegima "fi;\0" \ 63*1541d7a6SVanessa Maegima "netargs=setenv bootargs console=${console},${baudrate} " \ 64*1541d7a6SVanessa Maegima "root=/dev/nfs " \ 65*1541d7a6SVanessa Maegima "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 66*1541d7a6SVanessa Maegima "netboot=echo Booting from net ...; " \ 67*1541d7a6SVanessa Maegima "run netargs; " \ 68*1541d7a6SVanessa Maegima "if test ${ip_dyn} = yes; then " \ 69*1541d7a6SVanessa Maegima "setenv get_cmd dhcp; " \ 70*1541d7a6SVanessa Maegima "else " \ 71*1541d7a6SVanessa Maegima "setenv get_cmd tftp; " \ 72*1541d7a6SVanessa Maegima "fi; " \ 73*1541d7a6SVanessa Maegima "${get_cmd} ${image}; " \ 74*1541d7a6SVanessa Maegima "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 75*1541d7a6SVanessa Maegima "bootz ${loadaddr} - ${fdt_addr}; " \ 76*1541d7a6SVanessa Maegima "else " \ 77*1541d7a6SVanessa Maegima "echo WARN: Cannot load the DT; " \ 78*1541d7a6SVanessa Maegima "fi;\0" 79*1541d7a6SVanessa Maegima 80*1541d7a6SVanessa Maegima #define CONFIG_BOOTCOMMAND \ 81*1541d7a6SVanessa Maegima "if mmc rescan; then " \ 82*1541d7a6SVanessa Maegima "if run loadimage; then " \ 83*1541d7a6SVanessa Maegima "run mmcboot; " \ 84*1541d7a6SVanessa Maegima "else run netboot; " \ 85*1541d7a6SVanessa Maegima "fi; " \ 86*1541d7a6SVanessa Maegima "else run netboot; fi" 87*1541d7a6SVanessa Maegima 88*1541d7a6SVanessa Maegima #define CONFIG_SYS_MEMTEST_START 0x80000000 89*1541d7a6SVanessa Maegima #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) 90*1541d7a6SVanessa Maegima 91*1541d7a6SVanessa Maegima #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 92*1541d7a6SVanessa Maegima #define CONFIG_SYS_HZ 1000 93*1541d7a6SVanessa Maegima 94*1541d7a6SVanessa Maegima /* Physical Memory Map */ 95*1541d7a6SVanessa Maegima #define CONFIG_NR_DRAM_BANKS 1 96*1541d7a6SVanessa Maegima #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 97*1541d7a6SVanessa Maegima 98*1541d7a6SVanessa Maegima #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 99*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 100*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 101*1541d7a6SVanessa Maegima 102*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_SP_OFFSET \ 103*1541d7a6SVanessa Maegima (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 104*1541d7a6SVanessa Maegima #define CONFIG_SYS_INIT_SP_ADDR \ 105*1541d7a6SVanessa Maegima (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 106*1541d7a6SVanessa Maegima 107*1541d7a6SVanessa Maegima /* I2C configs */ 108*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C 109*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC 110*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C1 111*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C2 112*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C3 113*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C4 114*1541d7a6SVanessa Maegima #define CONFIG_SYS_I2C_SPEED 100000 115*1541d7a6SVanessa Maegima 116*1541d7a6SVanessa Maegima /* PMIC */ 117*1541d7a6SVanessa Maegima #define CONFIG_POWER 118*1541d7a6SVanessa Maegima #define CONFIG_POWER_I2C 119*1541d7a6SVanessa Maegima #define CONFIG_POWER_PFUZE3000 120*1541d7a6SVanessa Maegima #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 121*1541d7a6SVanessa Maegima 122*1541d7a6SVanessa Maegima /* FLASH and environment organization */ 123*1541d7a6SVanessa Maegima #define CONFIG_ENV_SIZE SZ_8K 124*1541d7a6SVanessa Maegima 125*1541d7a6SVanessa Maegima #define CONFIG_ENV_OFFSET (8 * SZ_64K) 126*1541d7a6SVanessa Maegima #define CONFIG_SYS_FSL_USDHC_NUM 2 127*1541d7a6SVanessa Maegima 128*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_ENV_DEV 0 129*1541d7a6SVanessa Maegima #define CONFIG_SYS_MMC_ENV_PART 0 130*1541d7a6SVanessa Maegima 131*1541d7a6SVanessa Maegima /* USB Configs */ 132*1541d7a6SVanessa Maegima #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 133*1541d7a6SVanessa Maegima #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 134*1541d7a6SVanessa Maegima #define CONFIG_MXC_USB_FLAGS 0 135*1541d7a6SVanessa Maegima #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 136*1541d7a6SVanessa Maegima 137*1541d7a6SVanessa Maegima #define CONFIG_IMX_THERMAL 138*1541d7a6SVanessa Maegima 139*1541d7a6SVanessa Maegima #define CONFIG_USB_FUNCTION_MASS_STORAGE 140*1541d7a6SVanessa Maegima 141*1541d7a6SVanessa Maegima #endif 142