179043d84SAkshay Saraswat /* 279043d84SAkshay Saraswat * Copyright (C) 2014 Samsung Electronics 379043d84SAkshay Saraswat * 479043d84SAkshay Saraswat * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. 579043d84SAkshay Saraswat * 679043d84SAkshay Saraswat * SPDX-License-Identifier: GPL-2.0+ 779043d84SAkshay Saraswat */ 879043d84SAkshay Saraswat 979043d84SAkshay Saraswat #ifndef __CONFIG_PEACH_PI_H 1079043d84SAkshay Saraswat #define __CONFIG_PEACH_PI_H 1179043d84SAkshay Saraswat 12d7e1f02eSSjoerd Simons #define MEM_LAYOUT_ENV_SETTINGS \ 13d7e1f02eSSjoerd Simons "bootm_size=0x10000000\0" \ 14d7e1f02eSSjoerd Simons "kernel_addr_r=0x22000000\0" \ 15d7e1f02eSSjoerd Simons "fdt_addr_r=0x23000000\0" \ 16d7e1f02eSSjoerd Simons "ramdisk_addr_r=0x23300000\0" \ 17d7e1f02eSSjoerd Simons "scriptaddr=0x30000000\0" \ 18d7e1f02eSSjoerd Simons "pxefile_addr_r=0x31000000\0" 19d7e1f02eSSjoerd Simons 2079043d84SAkshay Saraswat #include <configs/exynos5420-common.h> 2179043d84SAkshay Saraswat #include <configs/exynos5-dt-common.h> 22*bf637ea5SSimon Glass #include <configs/exynos5-common.h> 2379043d84SAkshay Saraswat 2443900da8SHyungwon Hwang #define CONFIG_SYS_SDRAM_BASE 0x20000000 2543900da8SHyungwon Hwang #define CONFIG_SYS_TEXT_BASE 0x23E00000 2643900da8SHyungwon Hwang #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) 2743900da8SHyungwon Hwang 2879043d84SAkshay Saraswat /* select serial console configuration */ 2979043d84SAkshay Saraswat #define CONFIG_SERIAL3 /* use SERIAL 3 */ 3043900da8SHyungwon Hwang #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" 3179043d84SAkshay Saraswat 3279043d84SAkshay Saraswat /* Display */ 3379043d84SAkshay Saraswat #ifdef CONFIG_LCD 3479043d84SAkshay Saraswat #define CONFIG_EXYNOS_FB 3579043d84SAkshay Saraswat #define CONFIG_EXYNOS_DP 3679043d84SAkshay Saraswat #define LCD_BPP LCD_COLOR16 3779043d84SAkshay Saraswat #endif 3879043d84SAkshay Saraswat 3979043d84SAkshay Saraswat #define CONFIG_POWER_TPS65090_EC 4079043d84SAkshay Saraswat 4143581c83SAkshay Saraswat /* DRAM Memory Banks */ 4243581c83SAkshay Saraswat #define CONFIG_NR_DRAM_BANKS 7 4343581c83SAkshay Saraswat #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ 4443581c83SAkshay Saraswat 4579043d84SAkshay Saraswat #endif /* __CONFIG_PEACH_PI_H */ 46