1 /* 2 * Copyright (C) Stefano Babic <sbabic@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 8 #ifndef __PCM058_CONFIG_H 9 #define __PCM058_CONFIG_H 10 11 #include <config_distro_defaults.h> 12 13 #ifdef CONFIG_SPL 14 #define CONFIG_SPL_YMODEM_SUPPORT 15 #define CONFIG_SPL_SPI_SUPPORT 16 #define CONFIG_SPL_SPI_LOAD 17 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 18 #include "imx6_spl.h" 19 #endif 20 21 #include "mx6_common.h" 22 23 /* Thermal */ 24 #define CONFIG_IMX_THERMAL 25 26 /* Serial */ 27 #define CONFIG_MXC_UART 28 #define CONFIG_MXC_UART_BASE UART2_BASE 29 #define CONFIG_CONSOLE_DEV "ttymxc1" 30 31 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 32 33 /* Early setup */ 34 #define CONFIG_BOARD_EARLY_INIT_F 35 #define CONFIG_BOARD_LATE_INIT 36 #define CONFIG_DISPLAY_BOARDINFO_LATE 37 38 39 /* Size of malloc() pool */ 40 #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) 41 42 /* Ethernet */ 43 #define CONFIG_FEC_MXC 44 #define CONFIG_MII 45 #define IMX_FEC_BASE ENET_BASE_ADDR 46 #define CONFIG_FEC_XCV_TYPE RGMII 47 #define CONFIG_ETHPRIME "FEC" 48 #define CONFIG_FEC_MXC_PHYADDR 3 49 50 #define CONFIG_PHYLIB 51 #define CONFIG_PHY_MICREL 52 #define CONFIG_PHY_KSZ9031 53 54 /* SPI Flash */ 55 #define CONFIG_MXC_SPI 56 #define CONFIG_SF_DEFAULT_BUS 0 57 #define CONFIG_SF_DEFAULT_CS 0 58 #define CONFIG_SF_DEFAULT_SPEED 20000000 59 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 60 61 /* I2C Configs */ 62 #define CONFIG_SYS_I2C 63 #define CONFIG_SYS_I2C_MXC 64 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ 65 #define CONFIG_SYS_I2C_SPEED 100000 66 67 #ifndef CONFIG_SPL_BUILD 68 #define CONFIG_CMD_NAND 69 /* Enable NAND support */ 70 #define CONFIG_CMD_NAND_TRIMFFS 71 #define CONFIG_NAND_MXS 72 #define CONFIG_SYS_MAX_NAND_DEVICE 1 73 #define CONFIG_SYS_NAND_BASE 0x40000000 74 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 75 #define CONFIG_SYS_NAND_ONFI_DETECTION 76 #endif 77 78 /* DMA stuff, needed for GPMI/MXS NAND support */ 79 #define CONFIG_APBH_DMA 80 #define CONFIG_APBH_DMA_BURST 81 #define CONFIG_APBH_DMA_BURST8 82 83 /* Filesystem support */ 84 #define CONFIG_LZO 85 #define CONFIG_CMD_UBIFS 86 #define CONFIG_CMD_MTDPARTS 87 #define CONFIG_MTD_PARTITIONS 88 #define CONFIG_MTD_DEVICE 89 #define MTDIDS_DEFAULT "nand0=nand" 90 #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" 91 92 /* Various command support */ 93 #define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ 94 #define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ 95 #define CONFIG_CMD_GSC 96 #define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ 97 #define CONFIG_CMD_UBI 98 #define CONFIG_RBTREE 99 100 /* Physical Memory Map */ 101 #define CONFIG_NR_DRAM_BANKS 1 102 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 103 104 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 105 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 106 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 107 108 #define CONFIG_SYS_INIT_SP_OFFSET \ 109 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_ADDR \ 111 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 112 113 /* MMC Configs */ 114 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 115 #define CONFIG_SYS_FSL_USDHC_NUM 1 116 117 /* Environment organization */ 118 #define CONFIG_ENV_IS_IN_SPI_FLASH 119 #define CONFIG_ENV_SIZE (16 * 1024) 120 #define CONFIG_ENV_OFFSET (1024 * SZ_1K) 121 #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) 122 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 123 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 124 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 125 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 126 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 127 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 128 CONFIG_ENV_SECT_SIZE) 129 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 130 131 #ifdef CONFIG_ENV_IS_IN_NAND 132 #define CONFIG_ENV_OFFSET (0x1E0000) 133 #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) 134 #endif 135 136 #endif 137