1876a25d2SStefano Babic /* 2876a25d2SStefano Babic * Copyright (C) Stefano Babic <sbabic@denx.de> 3876a25d2SStefano Babic * 4876a25d2SStefano Babic * SPDX-License-Identifier: GPL-2.0+ 5876a25d2SStefano Babic */ 6876a25d2SStefano Babic 7876a25d2SStefano Babic 8876a25d2SStefano Babic #ifndef __PCM058_CONFIG_H 9876a25d2SStefano Babic #define __PCM058_CONFIG_H 10876a25d2SStefano Babic 11876a25d2SStefano Babic #include <config_distro_defaults.h> 12876a25d2SStefano Babic 13876a25d2SStefano Babic #ifdef CONFIG_SPL 14876a25d2SStefano Babic #define CONFIG_SPL_SPI_LOAD 15876a25d2SStefano Babic #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 16876a25d2SStefano Babic #include "imx6_spl.h" 17876a25d2SStefano Babic #endif 18876a25d2SStefano Babic 19876a25d2SStefano Babic #include "mx6_common.h" 20876a25d2SStefano Babic 21876a25d2SStefano Babic /* Thermal */ 22876a25d2SStefano Babic #define CONFIG_IMX_THERMAL 23876a25d2SStefano Babic 24876a25d2SStefano Babic /* Serial */ 25876a25d2SStefano Babic #define CONFIG_MXC_UART 26876a25d2SStefano Babic #define CONFIG_MXC_UART_BASE UART2_BASE 27*12ca05a3SSimon Glass #define CONSOLE_DEV "ttymxc1" 28876a25d2SStefano Babic 29876a25d2SStefano Babic #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 30876a25d2SStefano Babic 31876a25d2SStefano Babic /* Early setup */ 32876a25d2SStefano Babic #define CONFIG_DISPLAY_BOARDINFO_LATE 33876a25d2SStefano Babic 34876a25d2SStefano Babic 35876a25d2SStefano Babic /* Size of malloc() pool */ 36876a25d2SStefano Babic #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) 37876a25d2SStefano Babic 38876a25d2SStefano Babic /* Ethernet */ 39876a25d2SStefano Babic #define CONFIG_FEC_MXC 40876a25d2SStefano Babic #define CONFIG_MII 41876a25d2SStefano Babic #define IMX_FEC_BASE ENET_BASE_ADDR 42876a25d2SStefano Babic #define CONFIG_FEC_XCV_TYPE RGMII 43876a25d2SStefano Babic #define CONFIG_ETHPRIME "FEC" 44876a25d2SStefano Babic #define CONFIG_FEC_MXC_PHYADDR 3 45876a25d2SStefano Babic 46876a25d2SStefano Babic /* SPI Flash */ 47876a25d2SStefano Babic #define CONFIG_MXC_SPI 48876a25d2SStefano Babic #define CONFIG_SF_DEFAULT_BUS 0 49876a25d2SStefano Babic #define CONFIG_SF_DEFAULT_CS 0 50876a25d2SStefano Babic #define CONFIG_SF_DEFAULT_SPEED 20000000 51876a25d2SStefano Babic #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 52876a25d2SStefano Babic 53876a25d2SStefano Babic /* I2C Configs */ 54876a25d2SStefano Babic #define CONFIG_SYS_I2C 55876a25d2SStefano Babic #define CONFIG_SYS_I2C_MXC 56876a25d2SStefano Babic #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ 57876a25d2SStefano Babic #define CONFIG_SYS_I2C_SPEED 100000 58876a25d2SStefano Babic 59876a25d2SStefano Babic #ifndef CONFIG_SPL_BUILD 60876a25d2SStefano Babic /* Enable NAND support */ 61876a25d2SStefano Babic #define CONFIG_SYS_MAX_NAND_DEVICE 1 62876a25d2SStefano Babic #define CONFIG_SYS_NAND_BASE 0x40000000 63876a25d2SStefano Babic #define CONFIG_SYS_NAND_5_ADDR_CYCLE 64876a25d2SStefano Babic #define CONFIG_SYS_NAND_ONFI_DETECTION 65876a25d2SStefano Babic #endif 66876a25d2SStefano Babic 67876a25d2SStefano Babic /* DMA stuff, needed for GPMI/MXS NAND support */ 68876a25d2SStefano Babic 69876a25d2SStefano Babic /* Filesystem support */ 70876a25d2SStefano Babic 71876a25d2SStefano Babic /* Physical Memory Map */ 72876a25d2SStefano Babic #define CONFIG_NR_DRAM_BANKS 1 73876a25d2SStefano Babic #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 74876a25d2SStefano Babic 75876a25d2SStefano Babic #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 76876a25d2SStefano Babic #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 77876a25d2SStefano Babic #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 78876a25d2SStefano Babic 79876a25d2SStefano Babic #define CONFIG_SYS_INIT_SP_OFFSET \ 80876a25d2SStefano Babic (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 81876a25d2SStefano Babic #define CONFIG_SYS_INIT_SP_ADDR \ 82876a25d2SStefano Babic (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 83876a25d2SStefano Babic 84876a25d2SStefano Babic /* MMC Configs */ 85876a25d2SStefano Babic #define CONFIG_SYS_FSL_ESDHC_ADDR 0 86876a25d2SStefano Babic #define CONFIG_SYS_FSL_USDHC_NUM 1 87876a25d2SStefano Babic 88876a25d2SStefano Babic /* Environment organization */ 89876a25d2SStefano Babic #define CONFIG_ENV_SIZE (16 * 1024) 90876a25d2SStefano Babic #define CONFIG_ENV_OFFSET (1024 * SZ_1K) 91876a25d2SStefano Babic #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) 92876a25d2SStefano Babic #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 93876a25d2SStefano Babic #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 94876a25d2SStefano Babic #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 95876a25d2SStefano Babic #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 96876a25d2SStefano Babic #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 97876a25d2SStefano Babic #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 98876a25d2SStefano Babic CONFIG_ENV_SECT_SIZE) 99876a25d2SStefano Babic #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 100876a25d2SStefano Babic 101876a25d2SStefano Babic #ifdef CONFIG_ENV_IS_IN_NAND 102876a25d2SStefano Babic #define CONFIG_ENV_OFFSET (0x1E0000) 103876a25d2SStefano Babic #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) 104876a25d2SStefano Babic #endif 105876a25d2SStefano Babic 106876a25d2SStefano Babic #endif 107