1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the phytec PCM-052 SoM. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_CACHELINE_SIZE 32 13 14 #include <asm/arch/imx-regs.h> 15 16 #define CONFIG_VF610 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 #define CONFIG_SYS_THUMB_BUILD 21 22 #define CONFIG_SKIP_LOWLEVEL_INIT 23 24 /* Enable passing of ATAGs */ 25 #define CONFIG_CMDLINE_TAG 26 27 /* Size of malloc() pool */ 28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 29 30 #define CONFIG_BOARD_EARLY_INIT_F 31 32 #define LPUART_BASE UART1_BASE 33 34 /* Allow to overwrite serial and ethaddr */ 35 #define CONFIG_ENV_OVERWRITE 36 #define CONFIG_SYS_UART_PORT (1) 37 #define CONFIG_BAUDRATE 115200 38 39 #undef CONFIG_CMD_IMLS 40 41 /* NAND support */ 42 #define CONFIG_CMD_NAND 43 #define CONFIG_CMD_NAND_TRIMFFS 44 #define CONFIG_SYS_NAND_ONFI_DETECTION 45 46 #ifdef CONFIG_CMD_NAND 47 #define CONFIG_USE_ARCH_MEMCPY 48 #define CONFIG_SYS_MAX_NAND_DEVICE 1 49 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 50 51 #define CONFIG_JFFS2_NAND 52 53 /* UBI */ 54 #define CONFIG_CMD_UBI 55 #define CONFIG_CMD_UBIFS 56 #define CONFIG_RBTREE 57 #define CONFIG_LZO 58 59 /* Dynamic MTD partition support */ 60 #define CONFIG_CMD_MTDPARTS 61 #define CONFIG_MTD_PARTITIONS 62 #define CONFIG_MTD_DEVICE 63 #define MTDIDS_DEFAULT "nand0=NAND" 64 #define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ 65 ",384k(bootloader)"\ 66 ",128k(env1)"\ 67 ",128k(env2)"\ 68 ",128k(dtb)"\ 69 ",6144k(kernel)"\ 70 ",65536k(ramdisk)"\ 71 ",450944k(root)" 72 #endif 73 74 #define CONFIG_MMC 75 #define CONFIG_FSL_ESDHC 76 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 77 #define CONFIG_SYS_FSL_ESDHC_NUM 1 78 79 /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ 80 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 81 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 82 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 83 84 #define CONFIG_CMD_MMC 85 #define CONFIG_GENERIC_MMC 86 #define CONFIG_CMD_FAT 87 #define CONFIG_DOS_PARTITION 88 89 #define CONFIG_CMD_PING 90 #define CONFIG_CMD_DHCP 91 #define CONFIG_CMD_MII 92 #define CONFIG_FEC_MXC 93 #define CONFIG_MII 94 #define IMX_FEC_BASE ENET_BASE_ADDR 95 #define CONFIG_FEC_XCV_TYPE RMII 96 #define CONFIG_FEC_MXC_PHYADDR 0 97 #define CONFIG_PHYLIB 98 #define CONFIG_PHY_MICREL 99 100 /* QSPI Configs*/ 101 102 #ifdef CONFIG_FSL_QSPI 103 #define CONFIG_CMD_SF 104 #define CONFIG_SPI_FLASH 105 #define FSL_QSPI_FLASH_SIZE (1 << 24) 106 #define FSL_QSPI_FLASH_NUM 2 107 #define CONFIG_SYS_FSL_QSPI_LE 108 #endif 109 110 /* I2C Configs */ 111 #define CONFIG_CMD_I2C 112 #define CONFIG_SYS_I2C 113 #define CONFIG_SYS_I2C_MXC_I2C3 114 #define CONFIG_SYS_I2C_MXC 115 116 /* RTC (actually an RV-4162 but M41T62-compatible) */ 117 #define CONFIG_CMD_DATE 118 #define CONFIG_RTC_M41T62 119 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 120 #define CONFIG_SYS_RTC_BUS_NUM 2 121 122 /* EEPROM (24FC256) */ 123 #define CONFIG_CMD_EEPROM 124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 126 #define CONFIG_SYS_I2C_EEPROM_BUS 2 127 128 #define CONFIG_BOOTDELAY 3 129 130 #define CONFIG_LOADADDR 0x82000000 131 132 /* We boot from the gfxRAM area of the OCRAM. */ 133 #define CONFIG_SYS_TEXT_BASE 0x3f408000 134 #define CONFIG_BOARD_SIZE_LIMIT 524288 135 136 #define CONFIG_BOOTCOMMAND "run bootcmd_sd" 137 #define CONFIG_EXTRA_ENV_SETTINGS \ 138 "fdt_high=0xffffffff\0" \ 139 "initrd_high=0xffffffff\0" \ 140 "blimg_file=u-boot.imx\0" \ 141 "blsec_addr=0x81000000\0" \ 142 "blimg_addr=0x81000400\0" \ 143 "kernel_file=zImage\0" \ 144 "kernel_addr=0x82000000\0" \ 145 "fdt_file=vf610-pcm052.dtb\0" \ 146 "fdt_addr=0x81000000\0" \ 147 "ram_file=uRamdisk\0" \ 148 "ram_addr=0x83000000\0" \ 149 "filesys=rootfs.ubifs\0" \ 150 "sys_addr=0x81000000\0" \ 151 "tftploc=/path/to/tftp/directory/\0" \ 152 "nfs_root=/path/to/nfs/root\0" \ 153 "tftptimeout=1000\0" \ 154 "tftptimeoutcountmax=1000000\0" \ 155 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 156 "bootargs_base=setenv bootargs rw mem=256M " \ 157 "console=ttyLP1,115200n8\0" \ 158 "bootargs_sd=setenv bootargs ${bootargs} " \ 159 "root=/dev/mmcblk0p2 rootwait\0" \ 160 "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ 161 "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ 162 "bootargs_nand=setenv bootargs ${bootargs} " \ 163 "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ 164 "bootargs_ram=setenv bootargs ${bootargs} " \ 165 "root=/dev/ram rw initrd=${ram_addr}\0" \ 166 "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 167 "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ 168 "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ 169 "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ 170 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 171 "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ 172 "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ 173 "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ 174 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 175 "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ 176 "nand read ${fdt_addr} dtb; " \ 177 "nand read ${kernel_addr} kernel; " \ 178 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 179 "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ 180 "nand read ${fdt_addr} dtb; " \ 181 "nand read ${kernel_addr} kernel; " \ 182 "nand read ${ram_addr} ramdisk; " \ 183 "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ 184 "update_bootloader_from_tftp=mtdparts default; " \ 185 "nand read ${blsec_addr} bootloader; " \ 186 "mw.b ${blimg_addr} 0xff 0x5FC00; " \ 187 "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ 188 "nand erase.part bootloader; " \ 189 "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ 190 "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ 191 "${kernel_file}; " \ 192 "then mtdparts default; " \ 193 "nand erase.part kernel; " \ 194 "nand write ${kernel_addr} kernel ${filesize}; " \ 195 "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ 196 "nand erase.part dtb; " \ 197 "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ 198 "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ 199 "then setenv fdtsize ${filesize}; " \ 200 "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ 201 "mtdparts default; " \ 202 "nand erase.part dtb; " \ 203 "nand write ${fdt_addr} dtb ${fdtsize}; " \ 204 "nand erase.part kernel; " \ 205 "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ 206 "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ 207 "then mtdparts default; " \ 208 "nand erase.part root; " \ 209 "ubi part root; " \ 210 "ubi create rootfs; " \ 211 "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ 212 "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ 213 "then mtdparts default; " \ 214 "nand erase.part ramdisk; " \ 215 "nand write ${ram_addr} ramdisk ${filesize}; fi\0" 216 217 /* Miscellaneous configurable options */ 218 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 219 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 220 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 221 #define CONFIG_AUTO_COMPLETE 222 #define CONFIG_CMDLINE_EDITING 223 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 224 #define CONFIG_SYS_PBSIZE \ 225 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 226 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 227 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 228 229 #define CONFIG_CMD_MEMTEST 230 #define CONFIG_SYS_MEMTEST_START 0x80010000 231 #define CONFIG_SYS_MEMTEST_END 0x87C00000 232 233 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 234 235 /* 236 * Stack sizes 237 * The stack sizes are set up in start.S using the settings below 238 */ 239 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 240 241 /* Physical memory map */ 242 #define CONFIG_NR_DRAM_BANKS 1 243 #define PHYS_SDRAM (0x80000000) 244 #define PHYS_SDRAM_SIZE (256 * 1024 * 1024) 245 246 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 247 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 248 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 249 250 #define CONFIG_SYS_INIT_SP_OFFSET \ 251 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 252 #define CONFIG_SYS_INIT_SP_ADDR \ 253 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 254 255 /* FLASH and environment organization */ 256 #define CONFIG_SYS_NO_FLASH 257 258 #ifdef CONFIG_ENV_IS_IN_MMC 259 #define CONFIG_ENV_SIZE (8 * 1024) 260 261 #define CONFIG_ENV_OFFSET (12 * 64 * 1024) 262 #define CONFIG_SYS_MMC_ENV_DEV 0 263 #endif 264 265 #ifdef CONFIG_ENV_IS_IN_NAND 266 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 267 #define CONFIG_ENV_SIZE (8 * 1024) 268 #define CONFIG_ENV_OFFSET 0xA0000 269 #define CONFIG_ENV_SIZE_REDUND (8 * 1024) 270 #define CONFIG_ENV_OFFSET_REDUND 0xC0000 271 #endif 272 273 #define CONFIG_OF_LIBFDT 274 #define CONFIG_CMD_BOOTZ 275 276 #endif 277